IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 164

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 9–10. Half-Rate Read Operation for HPC II—Non Burst-Aligned Address
Mem Command[2:0]
local_address[25:0]
AFI Memory Interface
AFI Command[2:0]
afi_rdata_valid[1:0]
local_rdata[31:0]
local_rdata_valid
afi_doing_rd[1:0]
local_burstbegin
mem_addr[13:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
local_read_req
afi_rdata[31:0]
local_size[4:0]
mem_cke[1:0]
afi_addr[27:0]
mem_cs_n[0]
mem_odt[1:0]
Controller - AFI
mem_ba[2:0]
mem_dq[7:0]
local_be[3:0]
afi_cs_n[3:0]
Local Interface
local_ready
afi_dm[3:0]
afi_ba[5:0]
mem_dqs
mem_dm
mem_clk
Half-Rate Read (Non Burst-Aligned Address)
phy_clk
00000 00001 00003 00005
2
[1]
0
0 0
00000
NOP
0000
NOP
10004 00000 20008 00000 3000C 00000 40010 00000 50014 00000 60018
RD
B
3
NOP
F
0
B
RD
3
0004 0000 0008 0000 000C 0000 0010 0000 0014 0000 0018
RD
00
NOP
F
0
NOP
RD
B
3
RD
NOP
[4]
F
0
NOP
[2]
RD
B
3
DD BB
CC
RD
AA
NOP
F
0
00
NOP
[3]
RD
B
3
11
00 FFEE
RD
NOP
F
0
00
NOP
00000
RD
B
3
DD BB
CC
RD
AA
NOP
00
NOP
11
00 FFEE
RD
00
DD BB CC
NOP
AABBCCDD
AABBCCDD
AA
3
AABBAABB
AABBAABB
0
EEFF0011
EEFF0011
3
EEFFEEFF
EEFFEEFF
0
F
AABBCCDD
AABBCCDD
[6]
3
AABBAABBEEFF0011
AABBAABB EEFF0011
[5]
0
3
EEFFEEFF
EEFFEEFF
0
F
AABBCCDD
AABBCCDD
3
00000
AABBAABB
AABBAABB
0
EEFF0011
EEFF0011
3
7