IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 125

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Block Description
December 2010 Altera Corporation
1. The ECC logic sends a read command to the partial write address.
2. Upon receiving a return data from the memory for the particular address, the ECC
3. The ECC logic issues a write to write back the updated data and the new ECC
The following corner cases can occur:
■
■
Figure 7–3
Figure 7–3. Partial Write for HPC II
Note to
(1) R represents the internal read-back memory data during the read-modify-write process.
Partial Bursts
DIMMs that do not have the DM pins do not support partial bursts. You must write a
minimum of eight words to the memory at the same time.
Figure 7–4
Figure 7–4. Partial Burst for HPC II
local_address
logic decodes the data, checks for errors, and then merges the corrected or correct
dataword with the incoming information.
code.
A single-bit error during the read phase of the read-modify-write process. In this
case, the single-bit error is corrected first, the single-bit error counter is
incremented and then a partial write is performed to this corrected decoded data
word.
A double-bit error during the read phase of the read-modify-write process. In this
case, the double-bit error counter is incremented and an interrupt is issued. A new
write word is written to the location of the error. The ECC status register keeps
track of the error information.
local_wdata
local_address
local_size
mem_dm
mem_dq
local_be
local_wdata
Figure
local_size
mem_dm
mem_dq
local_be
shows the partial write operation for HPC II.
shows the partial burst operation for HPC II.
7–3:
01234567
X1
0
01234567
2
X1
0
1
89ABCDEF
XF
1
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
67
External Memory Interface Handbook Volume 3
R
R
67
R
45
EF
CD
23
AB
01
89
7–9