IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 134

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–18
Table 7–8. ALTMEMPHY Debug Interface Signals
Register Maps Description
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
dbg_clk
dbg_addr
dbg_cs
dbg_wr
dbg_wr_data
dbg_rd
dbg_rd_data
dbg_waitrequest
Signal Name
Table 7–8
<variation_name>_phy.v/vhd file.
Table 7–9
Table 7–9. Register Map
ALTMEMPHY Register Map
Controller Register Map
Direction
Output
Input
Input
Input
Input
Input
Input
Input
shows the ALTMEMPHY Debug interface signals, which are located in
through
Address
0x005
0x006
0x100
0x110
0x120
0x121
0x122
0x123
0x124
0x125
0x126
0x130
0x131
0x132
Table 7–23
Debug interface clock
Debug interface address
Debug interface chip select
Debug interface write request
Debug interface write data
Debug interface read request
Debug interface read data
Debug interface wait request
show the register maps for the DDR3 SDRAM HPC II.
Mode register 0-1
Mode register 2-3
ALTMEMPHY status and control register
Controller status and configuration register
Memory address size register 0
Memory address size register 1
Memory address size register 2
Memory timing parameters register 0
Memory timing parameters register 1
Memory timing parameters register 2
Memory timing parameters register 3
ECC control register
ECC status register
ECC error address register
Chapter 7: Functional Description—High-Performance Controller II
Description
Contents
December 2010 Altera Corporation
Register Maps Description