IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 28

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–12
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
f
As shown in
1212.1 MHz, rather than the 1515 MHz of
step mismatch between the PLL generated by the Quartus II Fitter and the PHY
sequencer setup written in the RTL. Because the calibration process expects a common
step size, the resulting design does not function properly in either the prototype
FPGA or in the HardCopy device.
If you choose to prototype in a slower speed grade FPGA (C4) and target a HardCopy
device, you must generate the ALTMEMPHY IP for the mid-speed grade FPGA to
ensure that proper values are chosen for both the FPGA and HardCopy devices—this
applies whether a performance improvement is desired or not.
For information about HardCopy issues such as vertical I/O overhang, PLLs adjacent
to I/Os, performance improvement, and timing closure, refer to
I/O Features
I/O Features
Table
in the HardCopy III Device Handbook, Volume 1, and
in the HardCopy IV Device Handbook, Volume 1.
2–9, the Quartus II Fitter restricts the VCO operating range to
Table
2–8. This restriction produces a phase
HardCopy Device Migration Guidelines
December 2010 Altera Corporation
HardCopy IV Device
HardCopy III Device
Chapter 2: Getting Started