IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 131

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
Table 7–5. Local Interface Signals (Part 2 of 3)
December 2010 Altera Corporation
local_read_req
local_refresh_req
local_refresh_chip
local_size[]
local_wdata[]
local_write_req
local_multicast
local_self_rfsh_req
local_init_done
Signal Name
Input
Input
Direction
Output
Input
Input
Input
Input
Input
Input
Read request signal. You cannot assert the read request signal before the
reset_phy_clk_n signal goes high.
User-controlled refresh request. If Enable User Auto-Refresh Controls
option is turned on, local_refresh_req becomes available and you are
responsible for issuing sufficient refresh requests to meet the memory
requirements. This option allows complete control over when refreshes are
issued to the memory including grouping together multiple refresh
commands. Refresh requests take priority over read and write requests,
unless the requests are already being processed.
Controls which chip to issue the user-refresh to. This active high signal is
used together with the local_refresh_req signal. This signal is as wide as
the memory chip select. This signal asserts a high value to each bit that
represents the refresh for the corresponding memory chip. For example: If
the local_refresh_chip signal is assigned with a value of 4’b0101, the
controller refreshes the memory chips 0 and 2, and memory chips 1 and 3
are not refreshed.
If you turn on the Enable Multi-cast Write Control option, this signal is
ignored.
Controls the number of beats in the requested read or write access to
memory, encoded as a binary number. The range of supported Avalon burst
lengths is 1 to 64. The width of this signal is derived based on the burst count
specified in the Local Maximum Burst Count option. With the derived width,
you choose a value ranging from 1 to the local maximum burst count
specified.
Write data bus. The width of local_wdata is four times the memory data
bus for a half rate controller.
Write request signal. You cannot assert the write request signal before the
reset_phy_clk_n signal goes high.
In-band multi-cast write request signal. This active high signal is used
together with the local_write_req signal. When this signal is asserted
high, data is written to all the memory chips available.
option is enabled, you can request that the controller place the memory
devices into a self-refresh state by asserting this signal. The controller places
the memory in the self-refresh state as soon as it can without violating the
relevant timing parameters and responds by asserting the
local_self_rfsh_ack signal. You can hold the memory in the self-refresh
state by keeping this signal asserted. You can release the memory from the
self-refresh state at any time by deasserting the local_self_rfsh_req
signal and the controller responds by deasserting the
local__self_rfsh_ack signal once it has successfully brought the
memory out of the self-refresh state.
When the memory initialization, training, and calibration are complete, the
ALTMEMPHY sequencer asserts the ctrl_usr_mode_rdy signal to the
memory controller, which then asserts this signal to indicate that the memory
interface is ready to be used.
Read and write requests are still accepted before local_init_done is
asserted, however they are not issued to the memory until it is safe to do so.
This signal does not indicate that the calibration is successful.
User control of the self-refresh feature. If Enable Self-Refresh Controls
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Description
External Memory Interface Handbook Volume 3
7–15