IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 143

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
1
Latency is defined using the local (user) side frequency and absolute time (ns). There
are two types of latencies that exists while designing with memory controllers—read
and write latencies, which have the following definitions:
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For a half-rate controller, the local side frequency is half of the memory interface
frequency.
Altera defines read and write latencies in terms of the local interface clock frequency
and by the absolute time for the memory controllers. These latencies apply to
supported device families with the half-rate DDR3 high-performance controllers
(HPC and HPC II).
The latency defined in this section uses the following assumptions:
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The latency for the high-performance controller comprises many different stages of
the memory interface.
Read latency—the amount of time it takes for the read data to appear at the local
interface after initiating the read request.
Write latency—the amount of time it takes for the write data to appear at the
memory interface after initiating the write request.
The row is already open, there is no extra bank management needed.
The controller is idle, there is no queued transaction pending, indicated by the
local_ready signal asserted high.
No refresh cycles occur before the transaction.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
8. Latency