IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 47

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Compiling the Design
December 2010 Altera Corporation
After setting the parameters for the MegaCore function, you can now integrate the
MegaCore function variation into your design, and compile and simulate your design.
The following sections detail the steps you need to perform to compile and simulate
your design.
Figure 4–1
as an example of how your final design looks after you integrate the controller and the
user logic.
Figure 4–1. High-Performance Controller System-Level Diagram
Note to
(1) When you choose Instantiate DLL Externally, DLL is instantiated outside the controller.
Before compiling a design with the ALTMEMPHY variation, you must edit some
project settings, include the .sdc file, and make I/O assignments. I/O assignments
include I/O standard, pin location, and other assignments, such as termination and
drive strength settings. Some of these tasks are listed in the ALTMEMPHY
Generation window. For most systems, Altera recommends that you use the
Advanced I/O Timing feature by using the Board Trace Model command in the
Quartus II software to set the termination and output pin loads for the device.
To use the Quartus II software to compile the example top-level file in the Quartus II
software and perform post-compilation timing analysis, perform the following steps:
1. Set up the TimeQuest timing analyzer:
a. On the Assignments menu, click Timing Analysis Settings, select Use
b. Add the Synopsys Design Constraints (.sdc) file,
c. Add the .sdc file for the example top-level design,
Figure
TimeQuest Timing Analyzer during compilation, and click OK.
<variation name>_phy_ddr_timing.sdc, to your project. On the Project menu,
click Add/Remove Files in Project and browse to select the file.
<variation name>_example_top.sdc, to your project. This file is only required if
you are using the example as the top-level design.
External
Memory
Device
shows the top-level view of the Altera high-performance controller design
4–1:
ALTMEMPHY
DLL
PLL
(1)
Example Top-Level File
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
4. Compiling and Simulating
Performance
Controller
High-
External Memory Interface Handbook Volume 3
Example
Driver
Pass or Fail