IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 144

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

8–2
Figure 8–1. Typical Latency Path
Table 8–1. High-Performance Controller Latency Stages and Descriptions
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
T1
T2
T3
T4
T2 + T3
local_read_req
local_addr
Latency Number
Performance
local_rdata
Controller
Latency T1
phy_clk
High-
Controller
Command Output
CAS or WL
ALTMEMPHY
read data input
Write data latency
Figure 8–1
from the time a local_read_req assertion is detected by the controller up to data
available to be read from the dual-port RAM (DPRAM) module.
Table 8–1
that
From
four components:
Similarly, the write latency in the high-performance controllers is made up of three
components:
control_doing_rd
read latency = controller latency (T1) + command output latency (T2) +
CAS latency (T3) + PHY read data input latency (T4)
write latency = controller latency (T1) + write data latency (T2+T3)
Figure 8–1
Latency Stage
Figure
shows the different stages that make up the whole read and write latency
DPRAM
shows a typical memory interface read latency path showing read latency
8–1, the read latency in the high-performance controllers is made up of
Address/Command Generation
shows.
Read Datapath
Half-
rate
0° or 180°
PLL
Core
local_read_req or local_write_req signal assertion to
ddr_cs_n signal assertion.
ddr_cs_n signal assertion to mem_cs_n signal assertion.
Read command to DQ data from the memory or write command to DQ
data to the memory.
Read data appearing on the local interface.
Write data appearing on the memory interface.
PHY
Synchronization
Alignment and
Resynchronization
Clock
I/O
Latency T2
PLL
Capture
FPGA Device
DQS Clock
Latency T4
Shifted
DQS Clk
Shifted
Description
December 2010 Altera Corporation
mem_clk_n [ ]
mem_dqs [ ]
mem_dq [ ]
mem_clk [ ]
mem_cs_n
Chapter 8: Latency
Memory Device
(includes CAS
Latency T3
latency)