IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 117

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Upgrading from HPC to HPC II
December 2010 Altera Corporation
The high-performance controller II (HPC II) architecture is an upgraded controller
with higher efficiency and more features than the HPC. HPC II is recommended for all
new designs.
HPC II is pin-out compatible with your existing DDR high-performance designs. HPC
II has the following additional features:
■
■
■
■
■
■
■
If you want to migrate your designs from the existing HPC to the more efficient
HPC II, you must do the following:
■
■
Higher efficiency with in-order read and write commands, and out-of-order bank
management commands
Run-time programmability to configure the behavior of the controller
Integrated burst adapter supporting a range of burst sizes on the local interface
Integrated ECC logic, supporting 40-bit and 72-bit interfaces with partial word
writes and optional write back on error
Reduced bank tracking for area optimization
Controller variable latency to enhance the performance of your design
Support for multi-rank UDIMM and RDIMM ports
In the Preset Editor dialog box, assign the following HPC II timing parameters to
match your memory specification. Set these parameters according to the memory
datasheet:
■
■
■
For example, for Micron DDR3-800 datasheet, t
HPC II replaces the port interface level for the AFI and Avalon interface without
requiring any top-level change.
t
t
t
FAW
RRD
RTP
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
High-Performance Controller II
7. Functional Description—
FAW
External Memory Interface Handbook Volume 3
=40 ns, t
RRD
=10 ns, t
RTP
=10 ns.