IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 119

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Block Description
Figure 7–2. DDR3 SDRAM HPC II Architecture Block Diagram
December 2010 Altera Corporation
Avalon-MM Data Slave Interface
Control Register
Figure 7–2
The blocks in
The Avalon-MM data slave interface accepts read and write requests from the
Avalon-MM master. The width of the data, local_wdata and local_rdata, is four
times the width of the external memory.
The local address width is sized based on the memory chip, row, bank, and column
address widths. For example:
■
Write Data
Table
Command
Queue
FIFO
For multiple chip select:
width = chip bits + row bits + bank bits + column – 2
Read Data
shows a block diagram of the DDR3 SDRAM HPC II architecture.
Figure 7–2 on page 7–3
Write Data
Management
ECC-enabled
Timer
Bank
Logic
Logic
Decoder and
Correction
Encoder
ECC
ECC
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Command-Issuing
are described in the following sections.
State Machine
ECC-enabled
External Memory Interface Handbook Volume 3
Timing Logic
Address and
Generation
Command
Write Data
Datapath
Datapath
Decode
ODT
Logic
Write
Read
PHY Register
Table
7–3