IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 68

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–16
Table 5–2. DDR3 SDRAM Clocking Stratix IV and Stratix III Devices (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
phy_clk_1x
and
aux_half_rate_clk
mem_clk_2x
aux_full_rate_clk
write_clk_2x
resync_clk_2x
measure_clk_1x
Clock Name
(1)
Table 5–2
C0
C1
C2
C3
C4
C5
Postscale
Counter
shows the PLL outputs and their usage for Stratix III and Stratix IV devices.
–40°
(with
leveling)
30°
(without
leveling)
0
0°
(with
leveling)
60°
(without
leveling)
0°
(with
leveling)
–90°
(without
leveling)
Calibrated
Calibrated
(Degrees)
Phase
Half-Rate
Full-Rate
Full-Rate
Full-Rate
Full-Rate
Half-Rate
Clock
Rate
Global
None
Regional
Regional
Regional
Special
(2)
Network
Clock
Type
The only clock parameterizable for the
ALTMEMPHY megafunction. With
phy_clk_1x the sequencer generates
another sc_clk_dp clock with this clock
that programs the scan chains of the I/O
elements. For more information on
changing the clock network type, refer to the
ALTMEMPHY Design Tutorials
volume 6 of the External Memory Interface
Handbook.
Generates mem_clk that provides the
reference clock for the DLL. A dedicated
routing resource exists from the PLL to the
DLL, which you select with the regional
routing resource for the mem_clk using the
following attribute in the HDL:
(-name global_signal dual_regional
_clock;
-to dll~DFFIN
-name global_signal off). If you use
an external DLL, apply this attribute
similarly to the external DLL.
A copy of mem_clk_2x that you can use in
other parts of your design.
This clock feeds the write leveling delay
chains that generate the DQ, DM, DQS, and
mem_clk signals.
This clock feeds the I/O clock divider that
then reads the data out of the DDIO pins. Its
phase is adjusted in the calibration process.
The design uses an inverted version of this
clock for postamble clocking.
This clock is for VT tracking. This
free-running clock measures relative phase
shifts between the internal clock(s) and
those being fed back through a mimic path.
As a result, you can track VT effects on the
FPGA and compensate for the effects.
Chapter 5: Functional Description—ALTMEMPHY
December 2010 Altera Corporation
Notes
Block Description
section in