IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 39

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–6. ALTMEMPHY PHY Settings (Part 1 of 2)
December 2010 Altera Corporation
Use dedicated PLL
outputs to drive
memory clocks
Dedicated memory
clock phase
Use differential DQS
Enable external access
to reconfigure PLL
prior to calibration
Parameter Name
PHY Settings
The V
If the output slew rate of the write data is different from 1V/ns, you have to first
derate the t
specification.
For a 2V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn slew rate:
For a 0.5V/ns DQ slew rate rising signal and 1V/ns DQS-DQSn slew rate:
Click Next or the PHY Settings tab to set the options described in
options are available if they apply to the target Altera device.
Applicable Device Families
HardCopy II and Stratix II
(prototyping for
HardCopy II)
HardCopy II and Stratix II
(prototyping for
HardCopy II)
Arria II GX, Stratix III, and
Stratix IV
HardCopy II, Stratix III, and
Stratix IV (prototyping for
HardCopy II)
t
200 ps
t
200 ps
t
200.5 ps
t
200 ps
t
ps
t
310 ps
DS
DH
DS
DH
DS
DH
REF
(V
(V
(V
(V
(V
(V
REF
REF
REF
referenced setup and hold signals for a rising edge are:
REF
REF
REF
DS
) = Base t
) = Base t
) = Base t
) = Base t
) = Base t
) = Base t
and t
DH
DS
DS
DS
DH
DH
DH
values, then translate these AC/DC level specs to V
+ delta t
+ delta t
+ delta t
+ delta t
+ delta t
+ delta t
This option is disabled for DDR3 SDRAM.
This option is disabled for DDR3 SDRAM.
This option is disabled for DDR3 SDRAM.
When enabling this option for HardCopy II, Stratix III, and Stratix IV
devices, the inputs to the ALTPLL_RECONFIG megafunction are
brought to the top level for debugging purposes.
This option allows you to reconfigure the PLL before calibration to
adjust, if necessary, the phase of the memory clock (mem_clk_2x)
before the start of the calibration of the resynchronization clock on
the read side. The calibration of the resynchronization clock on the
read side depends on the phase of the memory clock on the write
side.
DS
DS
DS
DH
DH
DH
+ (V
+ (V
+ (V
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
+ (V
+ (V
+ (V
IH
IH
IH
IH
IH
IH
(ac) – V
(ac) – V
(ac) – V
(dc) – V
(dc) – V
(dc) – V
REF
REF
REF
Description
REF
REF
REF
External Memory Interface Handbook Volume 3
)/slew_rate = 25 + 5 + 350 = 380
)/slew_rate = 25 + 0 + 175 =
)/slew_rate = 25 + 88 + 87.5 =
)/slew_rate = 100 + 10 + 200 =
)/slew_rate = 100 + 0 + 100 =
)/slew_rate = 100 + 50 + 50 =
Table
3–6. The
REF
3–11