IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 129

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
Table 7–4. Clock and Reset Signals (Part 2 of 2)
December 2010 Altera Corporation
aux_full_rate_clk
aux_half_rate_clk
dll_reference_clk
reset_request_n
soft_reset_n
oct_ctl_rs_value
oct_ctl_rt_value
dqs_delay_ctrl_import
Name
Direction
Output
Output
Output
Output
Input
Input
Input
Input
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at the same frequency as the external
memory interface. In half-rate mode, this clock is twice the frequency
of the phy_clk and can be used whenever a 2x clock is required. In
full-rate mode, this clock is driven by the same PLL output as the
phy_clk signal.
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at half the frequency as the external
memory interface. In full-rate mode, this clock is half the frequency of
the phy_clk and can be used, for example to clock the user side of a
half-rate bridge. In half-rate mode, or if the Enable Half Rate Bridge
option is turned on, this clock is driven by the same PLL output that
drives the phy_clk signal.
Reference clock to feed to an externally instantiated DLL.
Reset request output that indicates when the PLL outputs are not
locked. Use this signal as a reset request input to any system-level
reset controller you may have. This signal is always low when the PLL
is trying to lock, and so any reset logic using it is advised to detect a
reset request on a falling edge rather than by level detection.
Edge detect reset input intended for SOPC Builder use or to be
controlled by other system reset logic. It is asserted to cause a
complete reset to the PHY, but not to the PLL used in the PHY.
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol.
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol.
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the export port on the ALTMEMPHY
instance with a DLL to the import port on the other ALTMEMPHY
instance.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Description
External Memory Interface Handbook Volume 3
7–13