IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 11

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: About This IP
Unsupported Features
Table 1–3. DDR3 SDRAM HPC and HPC II Features (Part 2 of 2)
Unsupported Features
MegaCore Verification
Resource Utilization
December 2010 Altera Corporation
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulator
Notes to
(1) HPC II supports additive latency values greater or equal to t
(2) This feature is not supported with DDR3 SDRAM with leveling
Table
ALTMEMPHY Megafunction
1–3:
The DDR3 SDRAM Controller with ALTMEMPHY IP does not support the following
features:
■
■
Altera performs extensive random, directed tests with functional test coverage using
industry-standard Denali models to ensure the functionality of the DDR3 SDRAM
Controller with ALTMEMPHY IP.
The following sections show the resource utilization data for the ALTMEMPHY
megafunction, and the DDR3 high-performance controllers (HPC and HPC II).
Table 1–4
the AFI in the Quartus II software version 10.0 for the following devices:
■
■
■
Timing simulation.
Partial burst and unaligned burst in ECC and non-ECC mode when DM pins are
disabled.
Arria II GX (EP2AGX260FF35C4) devices
Stratix III (EP3SL110F1152C2) devices
Stratix IV (EP4SGX230HF35C2) devices
and
Features
Table 1–5
show the typical size of the ALTMEMPHY megafunction with
RCD
.
-1, in clock cycle unit (t
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
CK
).
External Memory Interface Handbook Volume 3
HPC
Controller Architecture
v
HPC II
v
1–5