IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 55

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
Block Description
December 2010 Altera Corporation
Calibration
f
The major advantage of the ALTMEMPHY megafunction is that it supports an initial
calibration sequence to remove process variations in both the Altera device and the
memory device. In Arria series and Stratix series devices, the DDR3 SDRAM
ALTMEMPHY calibration process centers the resynchronization clock phase into the
middle of the captured data valid window to maximize the resynchronization setup
and hold margin. During the user operation, the VT tracking mechanism eliminates
the effects of VT variations on resynchronization timing margin.
This section describes the calibration that the sequencer performs, to find the optimal
clock phase for the memory interface. The calibration sequence is similar across
families, but different depending on the following target memory interface:
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DDR3 SDRAM Without Leveling
The calibration process for the DDR3 SDRAM without leveling PHY includes the
following steps:
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For more detailed information about each calibration step, refer to the
section in volume 4 of the External Memory Interface Handbook.
DDR3 SDRAM Without Leveling
DDR3 SDRAM With Leveling
“Step 1: Memory Device Initialization”
“Step 2: Write Training Patterns”
“Step 3: Read Resynchronization (Capture) Clock Phase”
“Step 4: Read and Write Datapath Timing”
“Step 5: Address and Command Clock Cycle”
“Step 6: Postamble”
“Step 7: Prepare for User Mode”
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Debugging
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