IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 84

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–32
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1
For half-rate designs, the AFI allows the controller to issue reads and writes that are
aligned to either half-cycle of the half-rate phy_clk, which means that the datapaths
can support multiple data alignments—word-unaligned and word-aligned writes and
reads.
Figure 5–15. Half-Rate Write with Word-Unaligned Data
Figure 5–16. Half-Rate Write with Word-Aligned Data
After calibration process is complete, the sequencer sends the write latency in number
of clock cycles to the controller.
Figure 5–17
read and write examples the data is written to and read from the same address. In
each example, ctl_rdata and ctl_wdata are aligned with controller clock (ctl_clk)
cycles. All the data in the bit vector is valid at once. For comparison, refer
and
The ctl_doing_rd is represented as a half-rate signal when passed into the PHY.
Therefore, the lower half of this bit vector represents one memory clock cycle and the
upper half the next memory clock cycle.
word-unaligned reads as an example of two ctl_doing_rd bits are different.
Therefore, for each x16 device, at least two ctl_doing_rd bits need to be driven, and
two ctl_rdata_valid bits need to be interpreted.
The AFI has the following conventions:
ctl_wdata_valid
ctl_wdata_valid
ctl_dqs_burst
ctl_dqs_burst
ctl_wdata
Figure 5–20
ctl_wdata
Figure 5–15
ctl_clk
ctl_clk
and
Figure 5–18
that show the word-unaligned writes and reads.
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and
Figure 5–16
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10
10
a x
show word-aligned writes and reads. In the following
11
display the half-rate write operation.
11
cb
ba
Figure 5–20 on page 5–37
11
11
dc
01
01
xd
Chapter 5: Functional Description—ALTMEMPHY
December 2010 Altera Corporation
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PHY-to-Controller Interfaces
shows separated
Figure 5–19