IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 82

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–30
Table 5–5. Other Interface Signals (Part 4 of 4)
Table 5–6. Parameters
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
rsu_read_latency
rsu_no_dvw_err
rsu_grt_one_dvw_
err
Notes to
(1) The debug interface uses the simple Avalon-MM interface protocol.
(2) These ports exist in the Quartus II software, even though the debug interface is for Altera’s use only.
Parameter Name
DWIDTH_RATIO
LOCAL_IF_DWIDTH
MEM_IF_DWIDTH
MEM_IF_DQS_WIDTH
MEM_IF_ROWADDR_WIDTH
MEM_IF_BANKADDR_WIDTH
MEM_IF_CS_WIDTH
MEM_IF_DM_WIDTH
MEM_IF_DQ_PER_DQS
MEM_IF_CLK_PAIR_COUNT
Signal Name
Table
5–5:
Table 5–6
Output
Output
Output
Type
shows the parameters that
Description
The data width ratio from the local interface to the memory interface. DWIDTH_RATIO of
2 means full rate, while DWIDTH_RATIO of 4 means half rate.
The width of the local data bus must be quadrupled for half-rate and doubled for
full-rate.
The data width at the memory interface. MEM_IF_DWIDTH can have values that are
multiples of MEM_IF_DQ_PER_DQS.
The number of DQS pins in the interface.
The row address width of the memory device.
The bank address with the memory device.
The number of chip select pins in the interface. The sequencer only calibrates one chip
select pin.
The number of mem_dm pins on the memory interface.
The number of mem_dq[] pins per mem_dqs pin.
The number of mem_clk/mem_clk_n pairs in the interface.
Width
—
—
—
The rsu_read_latency output is then set to the read latency (in
phy_clk cycles) using the rsu_codvw_phase resynchronization
clock phase. If calibration is unsuccessful then this signal is
undefined.
If the sequencer sweeps the resynchronization clock across every
phase and does not see any valid data at any phase position, then
calibration fails and this output is set to 1.
If the sequencer sweeps the resynchronization clock across every
phase and sees multiple data valid windows, this is indicative of
unexpected read data (random bit errors) or an incorrectly
configured PLL that must be resolved. Calibration has failed and this
output is set to 1.
Table 5–3
through
Chapter 5: Functional Description—ALTMEMPHY
Description
Table 5–5
December 2010 Altera Corporation
refer to.
ALTMEMPHY Signals