IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 80

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–28
Table 5–5. Other Interface Signals (Part 2 of 4)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
dqs_delay_ctrl_impor
t
dqs_offset_delay_ctr
l_ width
dll_reference_ clk
User-Mode Calibration OCT Control Signals
oct_ctl_rs_value
oct_ctl_rt_value
Debug Interface Signals
dbg_clk
dbg_reset_n
dbg_addr
dgb_wr
dbg_rd
dbg_cs
dbg_wr_data
dbg_rd_data
dbg_waitrequest
PLL Reconfiguration Signals—Stratix III and Stratix IV Devices
pll_reconfig_enable
pll_phasecountersele
ct
pll_phaseupdown
pll_phasestep
pll_phase_done
I/O Delay Chain Signals—Stratix III, HardCopy III, and HardCopy IV Devices
Signal Name
(Note
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Output
Type
1),
(Note 2)
DQS_DELA
Y_CTL_WI
DTH
DQS_DELA
Y_CTL_WI
DTH
1
14
14
1
1
DBG_A_WI
DTH
1
1
1
32
32
1
1
4
1
1
1
Width
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the dqs_delay_ctrl_export port
on the ALTMEMPHY instance with a DLL to the
dqs_delay_ctrl_import port on the other ALTMEMPHY instance.
Connects to the DQS delay logic when dll_import_export is set
to IMPORT. Only connect if you are using a DLL offset, which can
otherwise be tied to zero. If you are using a DLL offset, connect this
input to the offset_ctrl_out output of the dll_offset_ctrl
block.
Reference clock to feed to an externally instantiated DLL. This clock
is typically from one of the PHY PLL outputs.
OCT RS value port for use with ALT_OCT megafunction if you want
to use OCT with user-mode calibration.
OCT RT value port for use with ALT_OCT megafunction if you want to
use OCT with user-mode calibration.
Debug interface clock.
Debug interface reset.
Address input.
Write request.
Read request.
Chip select.
Debug interface write data.
Debug interface read data.
Wait signal.
This signal enables the PLL reconfiguration I/O, and is used if the
user requires some custom PLL phase reconfiguration. It should
otherwise be tied low.
When pll_reconfig_enable is asserted, this input is directly
connected to the PLL's phasecounterselect input. Otherwise this
input has no effect.
When pll_reconfig_enable is asserted, this input is directly
connected to the PLL's phaseupdown input. Otherwise this input has
no effect.
When pll_reconfig_enable is asserted, this input is directly
connected to the PLL's phasestep input. Otherwise this input has
no effect.
Directly connected to the PLL's phase_done output.
Chapter 5: Functional Description—ALTMEMPHY
Description
December 2010 Altera Corporation
ALTMEMPHY Signals