IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 18

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–2
SOPC Builder Flow
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Specifying Parameters
f
The SOPC Builder flow offers the following advantages:
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■
■
The MegaWizard Plug-In Manager flow offers the following advantages:
■
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The SOPC Builder flow allows you to add the DDR3 SDRAM Controller with
ALTMEMPHY IP directly to a new or existing SOPC Builder system.
You can also easily add other available components to quickly create an SOPC Builder
system with a DDR3 SDRAM controller, such as the Nios
scatter-gather direct memory access (SDMA) controllers. SOPC Builder automatically
creates the system interconnect logic and system simulation environment.
For more information about SOPC Builder, refer to
Handbook. For more information about how to use controllers with SOPC Builder,
refer to the
Interface Handbook. For more information on the Quartus II software, refer to the
Quartus II Help.
To specify the parameters for the DDR3 SDRAM Controller with ALTMEMPHY IP
using the SOPC Builder flow, perform the following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
2. On the Tools menu, click SOPC Builder.
3. For a new system, specify the system name and language.
4. Add DDR3 SDRAM Controller with ALTMEMPHY to your system from the
5. Specify the required parameters on all pages in the Parameter Settings tab.
Generates simulation environment
Creates custom components and integrates them via the component wizard
Interconnects all components with the Avalon-MM interface
Allows you to design directly from the DDR3 SDRAM interface to peripheral
device or devices
Achieves higher-frequency operation
Wizard.
System Contents tab.
1
1
f
The DDR3 SDRAM Controller with ALTMEMPHY is in the SDRAM
folder under the Memories and Memory Controllers folder.
To avoid simulation failure, you must set Local-to-Memory Address
Mapping to CHP-BANK-ROW-COL if you select High Peformance
Controller II for Controller Architecture.
For detailed explanation of the parameters, refer to the
Settings” on page
ALTMEMPHY Design Tutorials
3–1.
section in volume 6 of the External Memory
volume 4
®
II processor and
December 2010 Altera Corporation
of the Quartus II
“Parameter
Chapter 2: Getting Started
SOPC Builder Flow