IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 76

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–24
Table 5–3. Interface to the DDR3 SDRAM Devices
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
mem_addr
mem_ba
mem_cas_n
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_dm
mem_dq
mem_dqs
mem_dqs_n
mem_odt
mem_ras_n
mem_reset_n
mem_we_n
mem_ac_parity
parity_error_n
Signal Name
1
(4)
(4)
Signals with the prefix mem_ connect the PHY with the memory device; ports with the
prefix ctl_ connect the PHY with the controller.
The signal lists include the following signal groups:
■
■
■
■
■
■
■
■
■
Output
Output
Output
Output
Bidirectional
Bidirectional
Output
Output
Bidirectional
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Output
I/O interface to the SDRAM devices
Clocks and resets
External DLL signals
User-mode calibration OCT control
Write data interface
Read data interface
Address and command interface
Calibration control and status interface
Debug interface
Type
MEM_IF_ROWADDR_WIDTH
MEM_IF_BANKADDR_WIDTH
1
MEM_IF_CS_WIDTH
MEM_IF_CLK_PAIR_COUNT
MEM_IF_CLK_PAIR_COUNT
MEM_IF_CS_WIDTH
MEM_IF_DM_WIDTH
MEM_IF_DWIDTH
MEM_IF_DWIDTH/
MEM_IF_DQ_PER_DQS
MEM_IF_DWIDTH/
MEM_IF_DQ_PER_DQS
MEM_IF_CS_WIDTH
1
1
1
1
1
Width
(Note 1)
(2)
The memory row and column address bus.
The memory bank address bus.
The memory column address strobe.
The memory clock enable.
The memory clock, positive edge clock.
The memory clock, negative edge clock.
The memory chip select signal.
The optional memory DM bus.
The memory bidirectional data bus.
The memory bidirectional data strobe bus.
The memory bidirectional data strobe bus.
The memory on-die termination control signal.
The memory row address strobe.
The memory reset signal. This signal is derived
from the PHY’s internal reset signal, which is
generated by gating the global reset, soft reset,
and the PLL locked signal.
The memory write enable signal.
The address or command parity signal
generated by the PHY and sent to the DIMM.
The active-low signal that is asserted when a
parity error occurs and stays asserted until the
PHY is reset.
Chapter 5: Functional Description—ALTMEMPHY
December 2010 Altera Corporation
Description
ALTMEMPHY Signals
(3)