IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 34

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–6
Table 3–3. DDR3 SDRAM Attributes Settings (Part 2 of 2)
Table 3–4. DDR3 SDRAM Initialization Options (Part 1 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Row address width
Bank address width
Chip selects per DIMM
DQ bits per DQS bit
Drive DM pins from FPGA
Maximum memory frequency
for CAS latency 5.0
Maximum memory frequency
for CAS latency 6.0
Maximum memory frequency
for CAS latency 7.0
Maximum memory frequency
for CAS latency 8.0
Maximum memory frequency
for CAS latency 9.0
Maximum memory frequency
for CAS latency 10.0
Note to
(1) The range values depend on the actual memory device used.
Memory burst length
Memory burst ordering
DLL precharge power down
Parameter Name
Parameter Name
Table
3–3:
Fast exit or Slow
4, 8, on-the-fly
Sequential or
Range
Yes or No
Interleaved
80–700
12–16
1 or 2
4 or 8
Range
exit
3
(1)
Units
MHz
bits
bits
bits
bits
—
Units
beats
—
—
Defines the number of row address bits for your
interface. If your DDR3 SDRAM device’s row address bus
is 12-bit wide, set the row address width to 13 and set the
13
unconnected to the memory device) in the top-level file.
Defines the number of bank address bits for your
interface.
Defines the number of chip selects on each DIMM in your
interface. Currently, calibration is done with all ranks but
you can only perform timing analysis with one
single-rank DIMM.
Defines the number of data (DQ) bits for each data strobe
(DQS) pin.
Specifies whether you are using DM pins for write
operation. Altera devices do not support DM pins with ×4
mode.
Specifies the frequency limits from the memory data
sheet per given CAS latency. The ALTMEMPHY
MegaWizard Plug-In Manager generates a warning if the
operating frequency with your chosen CAS latency
exceeds this number. The lowest frequency supported by
DDR3 SDRAM devices is 300 MHz.
Sets the number of words read or written per
transaction.
Controls the order in which data is transferred between
memory and the FPGA during a read transaction. For
more information, refer to the memory device
datasheet.
Sets the mode register setting to disable (Slow exit) or
enable (Fast exit) the memory DLL when CKE is
disabled.
th
bit to logic-level low (or leave the 13
Description
Description
December 2010 Altera Corporation
ALTMEMPHY Parameter Settings
Chapter 3: Parameter Settings
th
bit