IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 169

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
Figure 9–13. Half-Rate Write Operation for HPC II—With Gaps
December 2010 Altera Corporation
AFI Memory Interface
Mem Command[2:0]
afi_wdata_valid[1:0]
local_address[25:0]
AFI Command[2:0]
local_wdata[31:0]
local_burstbegin
Controller - AFI
mem_addr[13:0]
Local Interface
afi_dqs_burst[0]
afi_dqs_burst[1]
local_write_req
afi_wdata[31:0]
local_size[4:0]
mem_cke[1:0]
afi_addr[27:0]
mem_odt[1:0]
mem_cs_n[0]
mem_ba[2:0]
mem_dq[7:0]
local_be[3:0]
afi_cs_n[3:0]
afi_wlat[4:0]
local_ready
afi_dm[3:0]
afi_ba[5:0]
mem_dqs
mem_dm
mem_clk
phy_clk
Half-Rate Write With Gaps
The following sequence corresponds with the numbered items in
1. The user logic requests the first read by asserting the local_read_req signal, and
2. When the command queue is full, the controller deasserts the local_ready signal
3. The user logic asserts a second local_read_req signal with a size of 2 and address
4. The controller issues the first read memory command and address signals to the
5. The ALTMEMPHY megafunction issues the read command to the memory and
AABBCCDD
the size and address for this read. In this example, the request is a burst of length
of 2 to the local address 0×0000810. This local address is mapped to the following
memory address in half-rate mode:
mem_row_address = 0×0001
mem_col_address = 0×0010<<2 = 0×0040
mem_bank_address = 0×00
to indicate that the controller has not accepted the command. The user logic must
keep the read request, size, and address signal until the local_ready signal is
asserted again.
of 0×0000912.
ALTMEMPHY megafunction for it to send to the memory device.
captures the read data from the memory.
0000000
NOP
0
NOP
00
[1]
0000F1C
2
EEFF0011
F
40C1030
3F
B
WR
AABBCCDD
EEFF0011
[6]
NOP
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
F
1030
WR
7
[2]
[5]
AABBCCDD
F
[4]
External Memory Interface Handbook Volume 3
0
3
[3]
NOP
DD CC BB AA 11 00 FF EE
EEFF0011
Figure
F
0
9–12:
9–23
00