IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 107

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Block Description
December 2010 Altera Corporation
Table 6–6
Table 6–6. Interrupt Status Register
Table 6–7
Table 6–7. Interrupt Mask Register
Table 6–8
Table 6–8. Single-Bit Error Location Status Register
Bits N – 1 down to 0
Others
Others
Others
Bit
Bit
0
1
2
3
4
0
1
2
3
4
shows the interrupt status register.
shows the interrupt mask register.
shows the single-bit error location status register.
Bit
Single-bit error
Double-bit error
Maximum single-bit error
Maximum double-bit error
Double-bit error during
read-modify-write
Reserved
Single-bit error
Double-bit error
Maximum single-bit error
Maximum double-bit error
Double-bit error during
read-modify-write
Reserved
Name
Name
Interrupt
Reserved
Name
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
When 1, single-bit error occurred.
When 1, double-bit error occurred.
When 1, single-bit error maximum threshold
exceeded.
exceeded.
When 1, double-bit error occurred during a read
modify write condition. (partial write).
Reserved.
occurs during a normal or read-modify-write
condition (partial write).
When 0, interrupt when double-bit error occurs
during a normal or read-modify-write condition
(partial write).
threshold exceeding condition.
threshold exceeding condition.
occurs during a read-modify-write condition
(partial write).
When 0, interrupt when double-bit error occurs
during a read-modify-write condition (partial
write).
Reserved.
When 1, double-bit error maximum threshold
When 1, masks single-bit error.
When 1, masks interrupt when double-bit error
When 1, masks single-bit error maximum
When 1, masks double-bit error maximum
When 1, masks interrupt when double-bit error
When 0, no single-bit error; when 1, single-bit
error occurred in this 64-bit part.
Reserved.
External Memory Interface Handbook Volume 3
Description
Description
Description
6–13