IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 122

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–6
Table 7–1. ODT
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Note to
(1) The controller does not drive the ODT signals during read operation.
DIMM
1
2
Table
ODT Generation Logic
User-Controlled Side-Band Signals
7–1:
Single chip select
Single chip select
Dual chip select
Dual chip select
Chip Select
per DIMM
■
■
■
During read, the afi_doing_read signal generates the afi_rdata_valid signal and
controls the ALTMEMPHY postamble circuit.
The ODT generation logic generates the necessary ODT signals for DDR3 SDRAM
HPC II memory devices, based on the scheme recommended by Altera.
Table 7–1
The user-controlled side-band signals consists of the following signals.
User-Refresh Commands
The user-refresh command enables the request to place the memory into refresh
mode. The user-refresh control takes precedence over a read or write request. You can
issue up to nine consecutive refresh commands to the selected memory chips.
However, if you enable the multi-cast write feature, the user refresh commands are
always issued to all chips.
Multi-Cast Write
The multi-cast write request signal allows you to ask the controller to send the current
write requests to all the chip selects. This means that the write data is written to all the
ranks in the system. The multi-cast write feature is useful for t
you can cycle through chips to continuously read data without hitting t
multi-cast write is not supported for registered DIMM interfaces or when the ECC
logic is enabled.
afi_wdata_valid
afi_wdata
afi_dm
shows which ODT signal on the adjacent DIMM is enabled.
Write or Read On
mem_cs[0]
mem_cs[0]
mem_cs[1]
mem_cs[0]
mem_cs[1]
mem_cs[0]
mem_cs[1]
mem_cs[2]
mem_cs[3]
mem_odt[0] and mem_odt[1]
mem_odt[0] and mem_odt[1]
mem_odt[0] and mem_odt[2]
mem_odt[1] and mem_odt[3]
mem_odt[0] and mem_odt[2]
mem_odt[1] and mem_odt[3]
Chapter 7: Functional Description—High-Performance Controller II
ODT Enabled (Write)
mem_odt[0]
mem_odt[0]
mem_odt[1]
December 2010 Altera Corporation
RC
mitigation where
ODT Enabled (Read)
mem_odt[1]
mem_odt[0]
mem_odt[2]
mem_odt[3]
mem_odt[0]
mem_odt[1]
RC
—
—
—
Block Description
. The
(1)
(1)
(1)