IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 77

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
Table 5–3. Interface to the DDR3 SDRAM Devices
Table 5–4. AFI Signals (Part 1 of 3)
December 2010 Altera Corporation
mem_err_out_n
Notes to
(1) Connected to I/O pads.
(2) Refer to
(3) Output is for memory device, and input path is fed back to ALTMEMPHY megafunction for VT tracking.
(4) This signal is for Registered DIMMs only.
Clocks and Resets
pll_ref_clk
global_reset_n
soft_reset_n
reset_request_n
ctl_clk
ctl_reset_n
Other Signals
aux_half_rate_clk
aux_full_rate_clk
Signal Name
Table
Signal Name
Table 5–6
5–3:
(4)
for parameter description.
Input
Type
Input
Input
Input
Output
Output
Output
Output
Output
Type
1
1
1
1
1
1
1
1
1
Width
Width
(Note 1)
(1)
(2)
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The reference clock input to the PHY PLL.
Active-low global reset for PLL and all logic in the
PHY. A level set reset signal, which causes a
complete reset of the whole system. The PLL may
maintain some state information.
Edge detect reset input intended for SOPC Builder
use or to be controlled by other system reset logic.
Causes a complete reset of PHY, but not the PLL
used in the PHY.
Directly connected to the locked output of the PLL
and is intended for optional use either by automated
tools such as SOPC Builder or could be manually
ANDed with any other system-level signals and
combined with any edge detect logic as required
and then fed back to the global_reset_n input.
Reset request output that indicates when the PLL
outputs are not locked. Use this as a reset request
input to any system-level reset controller you may
have. This signal is always low while the PLL is
locking (but not locked), and so any reset logic
using it is advised to detect a reset request on a
falling-edge rather than by level detection.
Half-rate clock supplied to controller and system
logic. The same signal as the non-AFI phy_clk.
Reset output on ctl_clk clock domain.
In half-rate designs, a copy of the phy_clk_1x
signal that you can use in other parts of your
design, same as phy_clk port.
In full-rate designs, a copy of the mem_clk_2x
signal that you can use in other parts of your
design.
The signal sent from the DIMM to the PHY to
indicate that a parity error has occured for a
particular cycle.
External Memory Interface Handbook Volume 3
Description
Description
5–25