IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 148

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

9–2
Figure 9–1. Auto-Precharge Operation for HPC
Notes to
(1) The auto-precharge request goes high.
(2) The local_ready signal is asserted and remains high until the auto-precharge request goes low.
(3) A new row address begins.
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Figure
Auto-Precharge
Memory Command[2:0]
mem_local_addr[24:0]
local_bank_addr[2:0]
local_row_addr[13:0]
9–1:
local_col_addr[9:0]
local_autopch_req
mem_addr[13:0]
AFI Memory Interface
local_write_req
local_read_req
mem_dq[7:0]
Local Interface
local_ready
mem_clk_n
mem_cs_n
mem_dqsn
mem_dqs
mem_clk
The auto-precharge read and auto-precharge write commands allow you to indicate
to the memory device that this read or write command is the last access to the
currently open row. The memory device automatically closes (auto-precharges) the
page it is currently accessing so that the next access to the same bank is quicker. This
command is particularly useful for applications that require fast random accesses.
phy_clk
00
0003
NOP
004
WR
0000
008
00C
0004 0008 000C 0410
010
NOP
0C00100
000
WR
0002
0000
004
NOP
008
00C
December 2010 Altera Corporation
DDR3 High-Performance Controllers
[1] [2]
WR
0004 0008 000C 0410
00
010
Chapter 9: Timing Diagrams
[3]
0C00200
0003
000
NOP