IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 149

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
Figure 9–2. User-Refresh Operation for HPC
Notes to
(1) The local refresh request signal is asserted.
(2) The controller asserts the local_refresh_ack signal.
(3) The auto-refresh (ARF) command on the command bus.
December 2010 Altera Corporation
mem_local_refresh_req
Mem Command[2:0]
local_refresh_ack
local_refresh_ack
local_refresh_req
AFI Memory Interface
local_init_done
global_reset_n
Figure
Controller - AFI
Local Interface
local_ready
ddr_a[13:0]
ddr_ba[2:0]
User Refresh
ddr_cas_n
ddr_cke_h
ddr_ras_n
ddr_we_n
ddr_cke_l
ddr_cs_n
phy_clk
9–2:
Figure 9–2
when the controller issues refreshes to the memory. This feature allows better control
of worst case latency and allows refreshes to be issued in bursts to take advantage of
idle periods.
shows the user refresh control interface. This feature allows you to control
[1]
[2]
NOP
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
ARF
[3]
External Memory Interface Handbook Volume 3
NOP
9–3