IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 111

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
Table 6–12. Clock and Reset Signals (Part 2 of 2)
Table 6–13. Local Interface Signals (Part 1 of 4)
December 2010 Altera Corporation
oct_ctl_rs_value
oct_ctl_rt_value
dqs_delay_ctrl_import
local_address[]
local_be[]
Signal Name
Name
Table 6–13 on page 6–17
Direction
Input
Input
Direction
Input
Input
Input
Memory address at which the burst should start. The width of this bus is sized
using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 2
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 2
If the bank address is 3 bits wide, row is 14 bits wide and column is 10 bits
wide, then the local address is 25 bits wide. To map local_address to bank,
row and column address:
local_address is 25 bits wide
local_address[24:22] = bank address [2:0]
local_address[21:8] = row address [13:0]
local_address [7:0] = col_address[9:2]
The two least significant bits (LSB) of the column address on the memory side
are ignored, because the local data width is four times that of the memory data
bus width.
Byte enable signal, which you use to mask off individual bytes during writes.
local_be is active high; mem_dm is active low.
To map local_wdata and local_be to mem_dq and mem_dm, consider a
full-rate design with 32-bit local_wdata and 16-bit mem_dq.
Local_wdata = < 22334455 >< 667788AA >< BBCCDDEE >
Local_be
These values map to:
Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >
1
shows the DDR3 SDRAM HPC local interface signals.
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol.
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol.
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the export port on the ALTMEMPHY
instance with a DLL to the import port on the other ALTMEMPHY
instance.
You can get the information on address mapping from the
<variation_name>_example_top.v
= <
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1100
><
Description
Description
0110
External Memory Interface Handbook Volume 3
><
or vhd file.
1010
>
6–17