IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 109

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—High-Performance Controller
Example Top-Level File
December 2010 Altera Corporation
Example Driver
1
There are two Altera-generated memory models available—associative-array
memory model and full-array memory model.
The associative-array memory model (<variation name>_mem model.v) allocates
reduced set of memory addresses with a default depth of 2,048 or 2K address spaces.
This allocation allows for a larger memory array compilation and simulation which
enables you to easily reconfigure the depth of the associate array.
The full-array memory model (<variation name>_full_mem_model.v) allocates
memory for all addresses accessible by the DDR cores. This allocation makes it
impossible to simulate large memory (more than 2K address spaces) designs, because
simulators need more memory than what is available on a typical system.
Both the memory models display similar behaviors and have the same calibration
time.
The memory model, <variation name>_test_component.v/vhd, used in SOPC Builder
designs, is actually a variation of the full-array memory model. To ensure your
simulation works in SOPC Builder, use memory model with less than 512-Mbit
capacity.
The example driver is a self-checking test pattern generator for the memory interface.
It uses a state machine to write and read from the memory to verify that the interface
is operating correctly.
It performs the following tests and loops back the tests indefinitely:
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■
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Sequential addressing writes and reads
The state machine writes pseudo-random data generated by a linear feedback shift
register (LFSR) to a set of incrementing row, bank, and column addresses. The
state machine then resets the LFSR, reads back the same set of addresses, and
compares the data it receives against the expected data. You can adjust the length
and pattern of the bursts that are written by changing the MAX_ROW, MAX_BANK, and
MAX_COL constants in the example driver source code, and the entire memory space
can be tested by adjusting these values. You can skip this test by setting the
test_seq_addr_on signal to logic zero.
Incomplete write operation
The state machine issues a series of write requests that are less than the maximum
burst size supported by your controller variation. The addresses are then read
back to ensure that the controller has issued the correct signals to the memory. This
test is only applicable when the local burst size is two. You can skip this test by
setting the test_incomplete_writes_on signal to logic zero.
Byte enable/data mask pin operation
The state machine issues two sets of write commands, the first of which clears a
range of addresses. The second set of write commands has only one byte enable bit
asserted. The state machine then issues a read request to the same addresses and
the data is verified. This test checks if the data mask pins are operating correctly.
You can skip this test by setting the test_dm_pin_on signal to logic zero.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
6–15