IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 38

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–10
Table 3–5. DDR3 SDRAM Timing Parameter Settings (Part 3 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
t
t
t
Note to
(1) See the memory device data sheet for the parameter range. Some of the parameters may be listed in a clock cycle (t
RRD
FAW
RTP
Plug-In Manager requires you to enter the value in a time unit (ps or ns), convert the number by multiplying it with the clock period of your
interface (and not the maximum clock period listed in the memory data sheet).
Parameter Name
Table
3–5:
1
Derating Memory Setup and Hold Timing
Because the base setup and hold time specifications from the memory device
datasheet assume input slew rates that may not be true for Altera devices, derate and
update the following memory device specifications in the Preset Editor dialog box:
■
■
■
■
For Arria II GX and Stratix IV devices, you need not derate using the Preset Editor.
You only need to enter the parameters referenced to V
automatically when you enter the slew rate information on the Board Settings tab.
After derating the values, you then need to normalize the derated value because
Altera input and output timing specifications are referenced to V
memory device setup and hold time numbers are derated and normalized to V
update these values in the Preset Editor dialog box to ensure that your timing
constraints are correct.
The following memory device specifications and update the Preset Editor dialog box
with the derated value:
For example, according to JEDEC, 533-MHz DDR3 SDRAM has the following
specifications, assuming 1V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn
slew rate:
■
■
■
■
■
■
t
t
t
t
Base t
Base t
V
V
V
V
DS
DH
IH
IS
IH
IH
IL
IL
(ac) = V
(dc) = V
(ac) = V
(dc) = V
2.06–64
7.69–256
2.06–64
DS
DH
= 25
Range
= 100
REF
REF
REF
REF
– 0.175 V
– 0.100 V
+ 0.175 V
+ 0.100 V
ns
ns
ns
Units
The activate to activate time, per device, RAS to RAS
delay timing parameter.
The four-activate window time, per device.
Read to precharge time.
(Note 1)
REF
Description
, and the deration is done
December 2010 Altera Corporation
ALTMEMPHY Parameter Settings
Chapter 3: Parameter Settings
REF
CK
) unit. If the MegaWizard
. When the
REF
,