IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 30

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–2
Table 3–1. General Settings
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Device family
Speed grade
PLL reference clock
frequency
Memory clock
frequency
Controller data rate
Enable half rate bridge
Local interface clock
frequency
Local interface width
Parameter Name
Memory Settings
1
The following sections describe the four tabs of the Parameter Settings page in more
detail.
In the Memory Settings tab, you can select a particular memory device for your
system and choose the frequency of operation for the device. Under General Settings,
you can choose the device family, speed grade, and clock information. In the middle
of the page (left-side), you can filter the available memory device listed on the right
side of the Memory Presets dialog box, refer to
exact device that you are using, choose a device that has the closest specifications,
then manually modify the parameters to match your actual device by clicking Modify
parameters, next to the Selected memory preset field.
Table 3–1
the ALTMEMPHY parameter editor.
When targeting a HardCopy device migration with performance improvement, the
ALTMEMPHY IP should target the mid speed grade to ensure that the PLL and the
PHY sequencer settings match. The compilation of the design can be executed in the
faster speed grade.
Targets device family (for example, Stratix III).
families. The device family selected here must match the device family selected on the MegaWizard
page 2a.
Selects a particular speed grade of the device (for example, 2, 3, or 4 for the Stratix III device
family).
Determines the clock frequency of the external input clock to the PLL. Ensure that you use three
decimal points if the frequency is not a round number (for example, 166.667 MHz or 100 MHz) to
avoid a functional simulation or a PLL locking problem.
Determines the memory interface clock frequency. If you are operating a memory device below its
maximum achievable frequency, ensure that you enter the actual frequency of operation rather than
the maximum frequency achievable by the memory device. Also, ensure that you use three decimal
points if the frequency is not a round number (for example, 333.333 MHz or 400 MHz) to avoid a
functional simulation or a PLL locking issue.
Selects the data rate for the memory controller. Sets the frequency of the controller to equal to
either the memory interface frequency (full-rate) or half of the memory interface frequency
(half-rate). The full-rate option is not available for DDR3 SDRAM devices.
This option is only available for HPC II full-rate controller.
Turn on to keep the controller in the memory full clock domain while allowing the local side to run
at half the memory clock speed, so that latency can be reduced.
Value that depends on the memory clock frequency and controller data rate, and whether or not
you turn on the Enable Half Rate Bridge option.
Value that depends on the memory clock frequency and controller data rate, and whether or not
you turn on the Enable Half Rate Bridge option.
describes the General Settings available on the Memory Settings page of
Description
Table 1–2 on page 1–3
Figure
3–1. If you cannot find the
December 2010 Altera Corporation
shows supported device
ALTMEMPHY Parameter Settings
Chapter 3: Parameter Settings