IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 44

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–16
Table 3–8. Controller Settings (Part 2 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Local maximum burst count
Controller latency
Enable configuration and
status register interface
Enable error detection and
correction logic
Enable auto error correction
Enable multi-cast write
control
Enable reduced bank tracking
for area optimization
Number of banks to track
Parameter
Controller Architecture
HPC II
HPC II
HPC II
HPC II
HPC II
HPC II
HPC II
Both
Specifies a burst count to configure the maximum Avalon burst
count that the controller slave port accepts.
Specifies a latency for the controller. The default latency is 5 but
you have the option to choose 4 to enhance the latency
performance of your design at the expense of timing closure.
Turn on to enable run-time configuration and status retrieval of
the memory controller. Enabling this option adds an additional
Avalon-MM slave port to the memory controller top level that
allows run-time reconfiguration and status retrieving for
memory timing parameters, memory address size and mode
register settings, and controller features. If the Error Detection
and Correction Logic option is enabled, the same slave port also
allows you to control and retrieve the status of this logic. Refer
to
page
Turn on to enable error correction coding (ECC) for single-bit
error correction and double-bit error detection. Refer to
Correction Coding (ECC)” on page 6–5
Correction Coding (ECC)” on page 7–7
Turn on to allow the controller to perform auto correction when
the ECC logic detects a single-bit error. Alternatively, you can
turn off this option and schedule the error correction at a
desired time for better system efficiency. Refer to
Correction Coding (ECC)” on page
Turn on to enable the multi-cast write control on the controller
top level. Asserting the multi-cast write control when requesting
a write burst causes the write data to be written to all the chip
selects in the memory system. When you turn on this option
together with the Enable User Auto-Refresh Controls option,
the user refresh commands are issued to all chips.
Multi-cast write is not supported for registered DIMM interfaces
or when you turn on the Enable Error Detection and Correction
Logic option.
Turn on to reduce the controller’s resource usage. By turning on
this option, you reduce the number of bank tracking blocks in
the controller. Refer to
for more information.
Specifies the number of bank tracking blocks you want for your
design. This option is only available if you turn on the Enable
Reduced Bank Tracking for Area Optimization option. The value
for this option depends on the value you specify for the
Command Queue Look-Ahead Depth option. Refer to
Management Logic” on page 7–4
“Configuration and Status Register (CSR) Interface” on
7–7.
DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings
“Bank Management Logic” on page 7–4
Description
for more information.
December 2010 Altera Corporation
7–7.
Chapter 3: Parameter Settings
for HPC, and
for HPC II.
“Error
“Error
“Bank
“Error