IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 92

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–40
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The ALTMEMPHY provides a signal, ctl_rdata_valid, to indicate that the data on
read data bus is valid. The width of this signal varies between half-rate and full-rate
designs to support the option to indicate that the read data is not word aligned.
Figure 5–21
Figure 5–21. Address and Command and Read-Path Timing—Full-Rate Design
Figure 5–22. Second Read Alignment—Half-Rate Design
Handshake Mechanism Between Write Commands and Write Data
In the AFI, the ALTMEMPHY output ctl_wlat gives the number of ctl_clk cycles
between the write command that is issued ctl_cs_n asserted and ctl_dqs_burst
asserted. The ctl_wlat signal considers the following actions to provide a single
value in ctl_clk clock cycles:
■
■
■
■
■
CAS write latency
Additive latency
Datapath latencies and relative phases
Board layout
Address and command path latency and 1T register setting, which is dynamically
setup to take into account any leveling effects
ctl_doing_read
ctl_rdata_valid
ctl_doing_read
ctl_rdata_valid
mem_dqs
mem_dqs
mem_dq
ctl_rdata
mem_dq
ctl_rdata
ctl_cs_n
ctl_cs_n
ctl_addr
ctl_addr
ctl_clk
ctl_clk
and
Figure 5–22
A
10
XA
10
10
01
01
show these relationships.
1
1
2
2
3
3
4
4
ctl_rlat = 9
Chapter 5: Functional Description—ALTMEMPHY
ctl_rlat = 9
5
5
6
6
December 2010 Altera Corporation
7
7
10
DX
8
8
Using a Custom Controller
01
01
XD
9
9