IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 128

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–12
Top-level Signals Description
Table 7–4. Clock and Reset Signals (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
global_reset_n
pll_ref_clk
phy_clk
reset_phy_clk_n
Name
■
The example driver has four outputs that allow you to observe which tests are
currently running and if the tests are passing. The pass not fail (pnf) signal goes low
once one or more errors occur and remains low. The pass not fail per byte
(pnf_per_byte) signal goes low when there is incorrect data in a byte but goes back
high again once correct data is observed in the following byte. The test_status signal
indicates the test that is currently running, allowing you to determine which test has
failed. The test_complete signal goes high for a single clock cycle at the end of the set
of tests.
Table 7–3
Table 7–3. Test Status[] Bit Mapping
Table 7–4
Bit
0
1
2
3
4
5
6
Low-power mode operation
The example driver requests the controller to place the memory into power-down
and self-refresh states, and hold it in those states for the amount of time specified
by the COUNTER_VALUE signal. You can vary this value to adjust the duration the
memory is kept in the low-power states. This test is only available if your
controller variation enables the low-power mode option.
shows the bit mapping for each test status.
shows the clock and reset signals.
Direction
Output
Output
Input
Input
The asynchronous reset input to the controller. All other reset signals
are derived from resynchronized versions of this signal. This signal
holds the complete ALTMEMPHY megafunction, including the PLL, in
reset while low.
The reference clock input to PLL.
The system clock that the ALTMEMPHY megafunction provides to the
user. All user inputs to and outputs from the DDR3 HPC II must be
synchronous to this clock.
The reset signal that the ALTMEMPHY megafunction provides to the
user. It is asserted asynchronously and deasserted synchronously to
phy_clk clock domain.
Test
Sequential address test
Incomplete write test
Data mask pin test
Address pin test
Power-down test
Self-refresh test
Auto precharge test
Chapter 7: Functional Description—High-Performance Controller II
Description
December 2010 Altera Corporation
Top-level Signals Description