IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 78

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–26
Table 5–4. AFI Signals (Part 2 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
aux_scan_clk
aux_scan_clk_reset_n
Write Data Interface
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata
ctl_dm
ctl_wlat
Read Data Interface
ctl_doing_rd
ctl_rdata
Signal Name
Output
Output
Input
Input
Input
Input
Output
Input
Output
Type
1
1
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
MEM_IF_DWIDTH ×
DWIDTH_RATIO
MEM_IF_DM_WIDTH ×
DWIDTH_RATIO
5
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
DWIDTH_RATIO ×
MEM_IF_DWIDTH
Width
(1)
Low frequency scan clock supplied primarily to
clock any user logic that interfaces to the PLL and
DLL reconfiguration interfaces.
This reset output asynchronously asserts (drives
low) when global_reset_n is asserted and
de-assert (drives high) synchronous to
aux_scan_clk when global_reset_n is
de-asserted. It allows you to reset any external
circuitry clocked by aux_scan_clk.
When asserted, mem_dqs is driven. The
ctl_dqs_burst signal must be asserted before the
ctl_wdata_valid signal and must be driven for
the correct duration to generate a correctly timed
mem_dqs signal.
Write data valid. Generates ctl_wdata and ctl_dm
output enables.
Write data input from the controller to the PHY to
generate mem_dq.
DM input from the controller to the PHY.
Required write latency between address/command
and write data that is issued to ALTMEMPHY
controller local interface.
This signal is only valid when the ALTMEMPHY
sequencer successfully completes calibration, and
does not change at any point during normal
operation.
The legal range of values for this signal is 0 to 31;
and the typical values are between 0 and ten, 0
mostly for low CAS latency DDR memory types.
Doing read input. Indicates that the DDR3 SDRAM
controller is currently performing a read operation.
The controller generates ctl_doing_rd to the
ALTMEMPHY megafunction. The ctl_doing_rd
signal is asserted for one phy_clk cycle for every
read command it issues. If there are two read
commands, ctl_doing_rd is asserted for two
phy_clk cycles. The ctl_doing_rd signal also
enables the capture registers and generates the
ctl_mem_rdata_valid signal. The
ctl_doing_rd signal should be issued at the same
time the read command is sent to the ALTMEMPHY
megafunction.
Read data from the PHY to the controller.
Chapter 5: Functional Description—ALTMEMPHY
Description
December 2010 Altera Corporation
ALTMEMPHY Signals