IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 156

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 9–6. Initialization Timing for HPC
memory_0_0.addr[13:0]
memory_0_1.addr[13:0]
memory_0_0.dm_tdqs
memory_0_1.dm_tdqs
seq_pll_start_reconfig
memory_0_0.dq[7:0]
memory_0_1.ba[1:0]
memory_0_1.dq[7:0]
Initialization Timing
memory_0_0.cas_n
memory_0_0.dqs_n
memory_0_1.cas_n
memory_0_1.dqs_n
memory_0_0.ras_n
memory_0_1.ras_n
memory_0_0.we_n
memory_0_1.we_n
seq_ac_cas_n[1:0]
memory_0_0.ba[2]
memory_0_0.ba[1]
memory_0_0.ba[0]
memory_0_0.rst_n
memory_0_1.rst_n
memory_0_1.ba[0]
seq_pll_select[3:0]
seq_pll_inc_dec_n
seq_ac_ras_n[1:0]
memory_0_0.ck_n
memory_0_0.cs_n
memory_0_1.ck_n
memory_0_1.cs_n
seq_ac_we_n[1:0]
memory_0_0.dqs
memory_0_1.dqs
memory_0_0.cke
memory_0_1.cke
memory_0_0.odt
memory_0_1.odt
mem_dqs_n[1:0]
memory_0_0.ck
memory_0_1.ck
global_reset_n
phs_shft_busy
mem_dq[15:0]
mem_dqs[1:0]
pll_locked
[1]
[2]
3
3
3
[3]
[3]