IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 89

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
Figure 5–20. Word-Unaligned Reads
Notes to
(1) Similar to word-aligned reads, ctl_doing_rd is asserted one memory clock cycle before chip select (ctl_cs_n) is asserted, which for a
(2) The return pattern of ctl_rdata_valid is a delayed version of ctl_doing_rd. Advertised read latency (ctl_rlat) is the number of controller
(3) The read data (ctl_rdata) is spread over three controller clock cycles and in the pointed to vector only the upper half of the ctl_rdata bit vector
December 2010 Altera Corporation
ctl_rdata_valid
ctl_doing_rd
word-unaligned read is in the previous controller clock (ctl_clk) cycle. In this example the ctl_doing_rd signal is now spread over three
controller clock (ctl_clk) cycles, the high bits in the sequence '10','11','01','10','11','01' providing the required four memory clock cycles of
assertion for ctl_doing_rd for the two 4-beat reads in the full-rate memory clock domain, '011110','011110'.
clock (ctl_clk) cycles delay inserted between ctl_doing_rd and ctl_rdata_valid.
is valid (denoted by ctl_rdata_valid).
mem_cs_n
command
mem_dqs
ctl_cas_n
ctl_ras_n
ctl_we_n
mem_clk
mem_dq
ctl_rdata
ctl_cs_n
Memory
Interface
ctl_addr
ctl_rlat
ctl_dm
Figure
ctl_clk
ctl_ba
5–20:
00 00
00 00
11 11
10
10
ACT
0000000
10
11
01
11
(1)
10
10
11
01
FFFFFFFF
FFFFFFFF
00 00
00
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
15
RD
11
0
External Memory Interface Handbook Volume 3
10
11
01
(2)
10
(3)
11
01
0f0e0f0e
00
5–37