IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 58

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–6
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
When the data calibration phase is completed, the sequencer issues the mimic
calibration sequence every 128 ms.
During initial calibration, the mimic path is sampled using the measure clock
(measure_clk has a _1x or _2x suffix, depending whether the ALTMEMPHY is a
full-rate or half-rate design). The sampled value is then stored by the sequencer. After
a sample value is stored, the sequencer uses the PLL reconfiguration logic to change
the phase of the measure clock by one VCO phase tap. The control sequencer then
stores the sampled value for the new mimic path clock phase. This sequence
continues until all mimic path clock phase steps are swept. After the control
sequencer stores all the mimic path sample values, it calculates the phase which
corresponds to the center of the high period of the mimic path waveform. This
reference mimic path sampling phase is used during the VT tracking phase.
In user mode, the sequencer periodically performs a tracking operation as defined in
the tracking calibration description. At the end of the tracking calibration operation,
the sequencer compares the most recent optimum tracking phase against the reference
sampling phase. If the sampling phases do not match, the mimic path delays have
changed due to voltage and temperature variations.
When the sequencer detects that the mimic path reference and most recent sampling
phases do not match, the sequencer uses the PLL reconfiguration logic to change the
phase of the resynchronization clock by the VCO taps in the same direction. This
allows the tracking process to maintain the near-optimum capture clock phase setup
during data tracking calibration as voltage and temperature vary over time.
The relationship between the resynchronization or capture clock and the data valid
window is maintained by measuring the mimic path variations due to the VT
variations and applying the same variation to the resynchronization clock.
Mimic Path
The mimic path mimics the FPGA elements of the round-trip delay, which enables the
calibration sequencer to track delay variation due to VT changes during the memory
read and write transactions without interrupting the operation of the ALTMEMPHY
megafunction.
The assumption made about the mimic path is that the VT variation on the round trip
delay path that resides outside of the FPGA is accounted for in the board skew and
memory parameters entered in the MegaWizard Plug-In Manager. For the write
direction, any VT variation in the memory devices is accounted for by timing analysis.
Figure 5–3
the delay of the clock outputs to the memory as far as the pads of the FPGA and the
delay from the input DQS pads to a register in the FPGA core. During the tracking
operation, the sequencer measures the delay of the mimic path by varying the phase
of the measure clock. Any change in the delay of the mimic path indicates a
corresponding change in the round-trip delay, and a corresponding adjustment is
made to the phase of the resynchronization or capture clock.
shows the mimic path in Stratix II and Stratix II GX devices, which mimics
Chapter 5: Functional Description—ALTMEMPHY
December 2010 Altera Corporation
Block Description