IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 75

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
Figure 5–12. DDR3 SDRAM Write Datapath in Stratix IV and Stratix III Devices
ALTMEMPHY Signals
December 2010 Altera Corporation
mem_dq
f
HDR to DDR
Conversion
Figure 5–12
converted to DDR data within the IOE element using both the half-rate and full-rate
clocks.
The write datapath DDIO registers are clocked by the phy_clk_1x clock. The
write_clk_2x signal then clocks the alignment registers.
For more information about the I/O structure, refer to the External Memory Interface
chapter in the respective device family handbook.
Figure 5–13
controller during a (half rate, normally aligned) write operation. The PHY then issues
the write data as ABCD where a is the first data to be written to the memory. (ABCD
represent two beats of data each.) The ctl_wdata_valid signal in
the output enable for the DQ and DM pins.
Figure 5–13. Write Data Alignment from the DDR3 SDRAM Controller
This section describes the ALMEMPHY megafunction signals for DDR3 SDRAM
variants.
Table 5–3
Stratix III
IOE
ctl_wdata_valid
through
ctl_dqs_burst
shows the reordered or the reordered-and-delayed HDR data is then
shows how the write data, ctl_wdata signals should be aligned from the
ctl_wdata
write_clk_2x
phy_clk_1x
ctl_clk
wdp_wdata3_1x
wdp_wdata2_1x
wdp_wdata1_1x
wdp_wdata0_1x
Table 5–5
00
00
show the signals.
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10
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Data Ordering
ba
Data
Ordering
11
11
dc
External Memory Interface Handbook Volume 3
--
00
00
ctl_wdata[4n]
phy_clk_1x
Figure 5–13
[
shows
5–23