SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 321

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.4
20.4.1
20.4.2
20.5
20.5.1
20.5.2
6500C–ATARM–8-Feb-11
Product Dependencies
CRCCU Functional Description
Power Management
Interrupt Source
CRC Calculation Unit description
CRC Calculation Unit Operation
The CRCCU is clocked through the Power Management Controller (PMC), the programmer
must first configure the CRCCU in the PMC to enable the CRCCU clock.
The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU
interrupt requires programming the Interrupt Controller before configuring the CRCCU.
The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured
and activated, this CRC engine performs a checksum computation on a Memory Area. CRC
computation is performed from the LSB to MSB bit. Three different polynomials are available
CCIT802.3, CASTAGNOLI and CCIT16, see the bitfield description,
mial” on page
The CRCCU has a DMA controller that supports programmable CRC memory checks. When
enabled, the DMA channel reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped
in the internal SRAM. The addresses of these two registers are pointed at by the
CRCCU_DSCR register.
Figure 20-2. CRCCU Descriptor Memory Mapping
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the
transfer-completed interrupt enable.
335, for details.
CRCCU_DSCR+0x10
CRCCU_DSCR+0xC
CRCCU_DSCR+0x8
CRCCU_DSCR+0x0
CRCCU_DSCR+0x4
TR_ADDR
TR_CTRL
Reserved
Reserved
TR_CRC
Memory
SRAM
“PTYPE: Primitive Polyno-
SAM3S
321