SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 347

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22. Bus Matrix (MATRIX)
22.1
22.2
22.2.1
22.2.2
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
Matrix Masters
Matrix Slaves
The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multi-
ple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix
interconnects 4 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a
slave is one cycle except for the default master of the accessed slave which is connected
directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers
that allow to support application specific features.
The Bus Matrix of the SAM3S product manages 4 masters, which means that each master can
perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 22-1.
The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allow-
ing a different arbitration per slave.
Table 22-2.
Master 0
Master 1
Master 2
Master 3
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
Internal Flash
External Bus Interface
Peripheral Bridge
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
CRC Calculation Unit
SAM3S
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