ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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IMPORTANT NOTICE
Dear customer,
nd
As from August 2
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
Company name - NXP B.V. is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site -
http://www.nxp.com
Contact information - the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
is replaced with
http://www.stnwireless.com
, is now found at
http://www.stnwireless.com
www.stnwireless.com

ISP1760ET,557 Summary of contents

  • Page 1

    IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...

  • Page 2

    ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications Rev. 04 — 4 February 2008 1. General description The ISP1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic processor interface. It integrates one Enhanced Host ...

  • Page 3

    ... NXP Semiconductors I Generic processor interface, non-multiplexed and variable latency, with a configurable 32-bit or 16-bit external data bus; the processor interface can be defined as variable-latency or SRAM type (memory mapping) I Slave DMA support to reduce the load of the host system CPU during the data transfer ...

  • Page 4

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name Description ISP1760BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 ISP1760ET TFBGA128 plastic thin fine-pitch ball grid array package; 128 balls; body 9 ISP1760_4 Product data sheet Embedded Hi-Speed USB host controller Rev. 04 — ...

  • Page 5

    ... NXP Semiconductors 5. Block diagram 47, 49, 51, 52 78, 80 DATA[15:0]/DATA[31:0] 82, 84, 86, 87 98, 100 to 103, 105 17 A[17:1] 106 CS_N 107 RD_N 108 WR_N 112 IRQ 114 DREQ DACK 116 USB FULL-SPEED AND LOW-SPEED DATA PATH PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS ...

  • Page 6

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. ISP1760_4 Product data sheet 1 ISP1760BE 38 Pin configuration (LQFP128); top view ball A1 index area Pin configuration (TFBGA128); top view Rev. 04 — 4 February 2008 Embedded Hi-Speed USB host controller 102 65 004aaa505 ISP1760ET 004aaa550 © ...

  • Page 7

    ... NXP Semiconductors 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin LQFP128 TFBGA128 OC3_N 1 C2 REF5V 2 A2 TEST1 3 B2 GNDA 4 A1 REG1V8 CC(5V0 CC(5V0) GND(OSC REG3V3 CC(I/O) XTAL1 11 E1 XTAL2 12 F2 CLKIN 13 F1 GNDD 14 G3 GND(RREF1 RREF1 16 G1 [4] GNDA 17 H2 DM1 ...

  • Page 8

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 PSW2_N 28 M1 GND(RREF3 RREF3 30 N1 [6] GNDA 31 P2 DM3 32 P1 GNDA 33 R2 DP3 34 R1 PSW3_N 35 T1 GNDD 36 T2 DATA0 37 R3 DATA1 38 T3 DATA2 CC(I/O) DATA3 41 P5 DATA4 42 T5 DATA5 43 R5 GNDD ...

  • Page 9

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA9 49 T8 REG1V8 50 R8 DATA10 51 P9 DATA11 52 T9 GNDC 53 R9 DATA12 54 T10 GNDD 55 R10 DATA13 56 P11 DATA14 57 T11 DATA15 58 R11 V 59 T12 CC(I/O) DATA16 60 R12 DATA17 61 T13 DATA18 62 R13 GNDD ...

  • Page 10

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA21 66 R15 V 67 P15 CC(I/O) DATA22 68 T16 DATA23 69 R16 DATA24 70 P16 GNDD 71 N16 DATA25 72 N15 DATA26 73 M15 DATA27 74 M16 V 75 M14 CC(I/O) DATA28 76 L16 DATA29 77 L15 DATA30 78 K16 GNDD 79 K15 ...

  • Page 11

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 A2 84 H15 REG1V8 85 G16 A3 86 H14 A4 87 F16 GNDC 88 G15 A5 89 F15 GNDD 90 E16 A6 91 F14 A7 92 E15 A8 93 D16 V 94 D15 CC(I/ C16 A10 96 C15 A11 97 B16 A12 98 B15 ...

  • Page 12

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 CS_N 106 A12 RD_N 107 B12 WR_N 108 B11 GNDD 109 A11 BAT_ON_N 110 C10 n.c. 111 A10 IRQ 112 B10 n.c. 113 A9 DREQ 114 B9 V 115 C8 CC(I/O) DACK 116 ...

  • Page 13

    ... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 TEST7 126 A4 OC1_N 127 B3 OC2_N 128 A3 [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. [2] All ground pins should normally be connected to a common ground plane. [ input only output only; I/O = digital input/output open-drain output; AI/O = analog input/output analog input power ...

  • Page 14

    ... NXP Semiconductors 7. Functional description 7.1 ISP1760 internal architecture: advanced NXP slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced NXP slave host controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1760 is adapted from Universal Serial Bus Rev ...

  • Page 15

    ... NXP Semiconductors Fig 4. 7.1.1 Internal clock scheme and port selection The ISP1760 has three ports. Fig 5. Figure 5 enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports need not be externally pulled HIGH because there are internal pull-down resistors on each port that are enabled by default ...

  • Page 16

    ... NXP Semiconductors Table 3. Port connection scenarios Port configuration Port 1 One port (port 1) DP and DM are routed to USB connector One port (port 2) DP and DM are not connected (left open) One port (port 3) DP and DM are not connected (left open) Two ports (ports 1 ...

  • Page 17

    ... NXP Semiconductors A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB bus can span for few milliseconds before requiring further CPU intervention for data movement. ...

  • Page 18

    ... NXP Semiconductors • The address range of the internal RAM buffer is from 0400h to FFFFh. • The internal memory contains isochronous, interrupt and asynchronous PTDs, and respective defined payloads. • All accesses to the internal memory are double word aligned. • Internal memory address range calculation: Memory address = (CPU address Table 4 ...

  • Page 19

    ... NXP Semiconductors Both the CPU interface logic and the USB host controller require access to the internal ISP1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the CPU interface and the internal USB host controller ...

  • Page 20

    ... NXP Semiconductors Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch data. That is, the fetching of data is independent of the address on A[15:0] lines. – Write the starting (read) address 4100h and bank2 = 10 to the Memory register. ...

  • Page 21

    ... NXP Semiconductors The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1760 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, whenever the bus is released because DACK is de-asserted, without affecting the DMA transfer counter or the current address. Any memory area can be accessed by the system’ ...

  • Page 22

    ... NXP Semiconductors – Enable ENABLE_DMA (bit 1) of the DMA Configuration register to determine the assertion of DREQ immediately after setting the bit. After programming the preceding parameters, the system’s DMA may be enabled, waiting for the DREQ to start the transfer or immediate transfer may be started. ...

  • Page 23

    ... NXP Semiconductors • event of interrupt occurs but the respective bit in the Interrupt Enable register is not set, then the respective Interrupt register bit is set but the interrupt signal is not asserted. An interrupt will be generated when interrupt is enabled and the respective bit in the Interrupt Enable register is set. ...

  • Page 24

    ... NXP Semiconductors Table 5. PTD 7.5 Phase-Locked Loop (PLL) clock multiplier The internal PLL requires a 12 MHz input, which can MHz crystal MHz clock already existing in the system with a precision better than 50 ppm. This allows the use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI). ...

  • Page 25

    ... NXP Semiconductors The SUSPEND/WAKEUP_N pin is a 3-state output also an input to the internal wake-up logic. When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of the SUSPEND/WAKEUP_N pin: • remains pulled-up, no wake-up is generated because a HIGH is sensed by the internal wake-up circuit. ...

  • Page 26

    ... NXP Semiconductors 7.7 Overcurrent detection The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The main features of this circuit are self reporting, automatic resetting, low-trip time and low cost ...

  • Page 27

    ... NXP Semiconductors 7.8 Power supply Figure 8 Fig 8. Figure 9 Fig 9. 7.8.1 Hybrid mode Table 6 ISP1760_4 Product data sheet shows the ISP1760 power supply connection. ISP1760BE V CC(5V0 10, 40, 48, V CC(I/O) 59, 67, 75, 83, 94, 104, 115 REG1V8 85 REG1V8 5, 50, 118 REG3V3 9 The figure shows the LQFP pinout. For the TFBGA ballout, see A 4 ...

  • Page 28

    ... NXP Semiconductors Table 6. Voltage V CC(5V0) V CC(I/O) In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current CC(5V0) back on, before the resume programming sequence starts. Fig 10. Hybrid mode Table 7 Table 7. Pins DATA[31:0], A[17:1], TEST1, TEST2, TEST3, ...

  • Page 29

    ... NXP Semiconductors To give a better view of the functionality, dips and t4 to t5. If the dip too short, that is, < the internal POR pulse will not react and will remain LOW. The internal POR starts with t0. At t1, the detector will see the passing of the trip level and a delay element will add another t before it drops to 0 ...

  • Page 30

    ... NXP Semiconductors 8. Registers Table 8 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle. • Operational registers range from 0000h to 01FFh. Configuration registers range from 0300h to 03FFh ...

  • Page 31

    ... NXP Semiconductors Table 8. Address 0344h 0354h 0374h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. CAPLENGTH - Capability Length register (address 0000h) bit description ...

  • Page 32

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol PRR Reset 0 Access R Table 12. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.1.4 HCCPARAMS register The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register, and the bit allocation is given in Table 13 ...

  • Page 33

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 1 Access R Table 14. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2 EHCI operational registers 8.2.1 USBCMD register The USB Command (USBCMD) register indicates the command to be executed by the serial host controller ...

  • Page 34

    ... NXP Semiconductors Table 15. USBCMD - USB Command register (address 0020h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LHCR Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...

  • Page 35

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 18. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. ...

  • Page 36

    ... NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol reserved Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 20. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. ...

  • Page 37

    ... NXP Semiconductors Table 22. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2.6 PORTSC1 register The Port Status and Control (PORTSC) register (bit allocation: well reset by hardware only when the auxiliary power is initially applied or in response to a host controller reset. The initial conditions of a port are: • ...

  • Page 38

    ... NXP Semiconductors Table 24. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. [2] These fields read logic 0, if the PP (Port Power) bit in register PORTSC1 is logic 0. 8.2.7 ISO PTD Done Map register The bit description of the register is given in Table 25. ISO PTD Done Map register (address 0130h) bit description ...

  • Page 39

    ... NXP Semiconductors Table 26. ISO PTD Skip Map register (address 0134h) bit description Bit Symbol Access ISO_PTD_SKIP R/W _MAP[31:0] When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs ...

  • Page 40

    ... NXP Semiconductors When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit must not be normally set on the position indicated by NextPTDPointer ...

  • Page 41

    ... NXP Semiconductors 8.2.15 ATL PTD Last PTD register The bit description of the ATL PTD Last PTD register is given in Table 33. ATL PTD Last PTD register (address 0158h) bit description Bit Symbol Access Value ATL_PTD_LAST R/W _PTD[31:0] Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking that PTD category. Subsequently, the process will restart with the fi ...

  • Page 42

    ... NXP Semiconductors Table 35. Bit 8.3.2 Chip ID register Read this register to get the ID of the ISP1760. The upper word of the register contains the hardware version number and the lower word contains the chip ID. bit description of the register. ISP1760_4 Product data sheet HW Mode Control - Hardware Mode Control register (address 0300h) bit ...

  • Page 43

    ... NXP Semiconductors Table 36. Chip ID - Chip Identifier register (address 0304h) bit description Bit Symbol Access Value CHIPID[31:0] R 8.3.3 Scratch register This register is for testing and debugging purposes only. The value read back must be the same as the value that was written. The bit description of this register is given in Table 37 ...

  • Page 44

    ... NXP Semiconductors Table 39. Bit 8.3.5 DMA Configuration register The bit allocation of the DMA Configuration register is given in Table 40. DMA Configuration register (address 0330h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol ...

  • Page 45

    ... NXP Semiconductors Table 41. Bit 8.3.6 Buffer Status register The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is, ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets the Buffer Filled bit of a particular transfer in the Buffer Status register, the HC will start traversing through PTD headers that are not marked for skipping and are valid PTDs ...

  • Page 46

    ... NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 43. Bit 8.3.7 ATL Done Timeout register The bit description of the ATL Done Timeout register is given in Table 44. ATL Done Timeout register (address 0338h) bit description ...

  • Page 47

    ... NXP Semiconductors Table 45. Memory register (address 033Ch) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...

  • Page 48

    ... NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 48. Bit 8.3.10 DMA Start Address register This register defines the start address select for the DMA read and write operations. See Table 49 Table 49 ...

  • Page 49

    ... NXP Semiconductors Table 50. Bit 8.3.11 Power Down Control register This register is used to turn off power to the internal blocks of the ISP1760 to obtain maximum power savings. Table 51. Power Down Control register (address 0354h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol ...

  • Page 50

    ... NXP Semiconductors Table 52. [1] Bit CLK_OFF_ ISP1760_4 Product data sheet Power Down Control register (address 0354h) bit description Symbol Description Clock Off Counter: Determines the wake-up status duration after any COUNTER wake-up event before the ISP1760 goes back into suspend mode. This ...

  • Page 51

    ... NXP Semiconductors Table 52. [1] Bit [1] For a 32-bit operation, the default wake-up counter value For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization. 8.3.12 Port 1 Control register The values read from the lower 16 bits and the upper 16 bits of this register are always the same ...

  • Page 52

    ... NXP Semiconductors Table 54. [1] Bit [1] For correct port 1 initialization, write 0080 0018h to this register after power-on. 8.4 Interrupt registers 8.4.1 Interrupt register The bits of this register indicate the interrupt source, defining the events that determined the INT generation. Clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position ...

  • Page 53

    ... NXP Semiconductors Table 56. Bit ISP1760_4 Product data sheet Interrupt register (address 0310h) bit description Symbol Description reserved; write reset value ISO_IRQ ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination were completed ...

  • Page 54

    ... NXP Semiconductors Table 56. Bit 8.4.2 Interrupt Enable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 57. Interrupt Enable register (address 0314h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit ...

  • Page 55

    ... NXP Semiconductors Table 58. Bit 8.4.3 ISO IRQ Mask OR register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. See see Section ISP1760_4 Product data sheet Interrupt Enable register (address 0314h) bit description ...

  • Page 56

    ... NXP Semiconductors Table 59. ISO IRQ Mask OR register (address 0318h) bit description Bit Symbol Access ISO_IRQ_MASK R/W _OR[31:0] 8.4.4 INT IRQ Mask OR register Each bit of this register (see and is a hardware IRQ mask for each PTD done map. For details, see Table 60. ...

  • Page 57

    ... NXP Semiconductors Table 63. INT IRQ Mask AND register (address 0328h) bit description Bit Symbol Access INT_IRQ_MASK R/W _AND[31:0] 8.4.8 ATL IRQ Mask AND register Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Table 64 Table 64 ...

  • Page 58

    ... NXP Semiconductors Multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by endpoint data structures, until it reaches the end of the endpoint list. There are three endpoint lists: one for ISO endpoints, and the other for INTL and ATL endpoints ...

  • Page 59

    ... NXP Semiconductors Fig 13. NextPTD traversal rule ISP1760_4 Product data sheet START PTD SCHEDULE no PTD SKIPPED? CHECK FOR yes VALID AND ACTIVE BIT SET? START PTD no EXECUTION FOLLOW NEXT PTD POINTED BY NEXTPTD POINTER Rev. 04 — 4 February 2008 ISP1760 Embedded Hi-Speed USB host controller ...

  • Page 60

    High-speed bulk IN and OUT Table 65 shows the bit allocation of the high-speed bulk IN and OUT, bulk Transfer Descriptor. Table 65. High-speed bulk IN and OUT: bit allocation Bit ...

  • Page 61

    ... NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - — writes NextPTDPointer SW — writes [4:0] DW3 — sets HW — resets — writes — writes — writes SW — writes 59 reserved - — writes HW — ...

  • Page 62

    ... NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access Cerr[1:0] HW — writes SW — writes NakCnt[3:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred SW — writes [14:0] 0000 DW2 reserved - RL[3:0] SW — writes 24 reserved - DataStart SW — writes Address[15:0] ...

  • Page 63

    ... NXP Semiconductors Table 66. High-speed bulk IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets ISP1760_4 Product data sheet Embedded Hi-Speed USB host controller … ...

  • Page 64

    High-speed isochronous IN and OUT Table 67 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD). Table 67. High-speed isochronous IN and OUT: bit allocation Bit ...

  • Page 65

    ... NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ISOIN_5[3:0] HW — writes ISOIN_4[11:0] HW — writes ISOIN_3[11:0] HW — writes ISOIN_2[11:8] HW — writes DW5 ISOIN_2[7:0] HW — writes ISOIN_1[11:0] HW — writes ISOIN_0[11:0] HW — ...

  • Page 66

    ... NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access — sets — writes — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15: Frame[7:0] SW — writes DW1 reserved - — writes EPType[1:0] SW — writes Token[1:0] SW — ...

  • Page 67

    ... NXP Semiconductors Table 68. High-speed isochronous IN and OUT: bit description Bit Symbol Access NrBytesTo SW — writes Transfer[14: reserved - — resets SW — sets ISP1760_4 Product data sheet Embedded Hi-Speed USB host controller …continued Value Description - Number of Bytes Transferred: This field indicates the number of bytes that can be transferred by this data structure used to indicate the depth of the DATA fi ...

  • Page 68

    High-speed interrupt IN and OUT Table 69 shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD). Table 69. High-speed interrupt IN and OUT: bit allocation Bit ...

  • Page 69

    ... NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 INT_IN_5[3:0] HW — writes INT_IN_4[11:0] HW — writes INT_IN_3[11:0] HW — writes INT_IN_2[11:8] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[11:0] HW — writes ...

  • Page 70

    ... NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15:0] ...

  • Page 71

    ... NXP Semiconductors Table 70. High-speed interrupt IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets Table 71 ISP1760_4 Product data sheet …continued Value Description - Multiplier: This field is a multiplier counter used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution ...

  • Page 72

    Start and complete split for bulk Table 72 shows the bit allocation of Start Split (SS) and Complete Split (CS) for bulk, asynchronous Start Split and Complete Split (SS/CS) Transfer Descriptor (TD). Table 72. Start and complete split for ...

  • Page 73

    ... NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - — writes NextPTDPointer SW — writes [4:0] DW3 — sets HW — resets — writes — writes — writes SW — writes ...

  • Page 74

    ... NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol Access NrBytesTransferred HW — writes [14:0] DW2 reserved - RL[3:0] SW — writes 24 reserved - DataStartAddress SW — writes [15: reserved - DW1 HubAddress[6:0] SW — writes PortNumber[6:0] SW — writes SE[1:0] SW — writes 47 reserved - — writes ...

  • Page 75

    ... NXP Semiconductors Table 73. Start and complete split for bulk: bit description Bit Symbol Access NrBytesToTransfer SW — writes [14: reserved - — sets HW — resets Table 74. Bulk I/O I/O ISP1760_4 Product data sheet …continued Value Description - Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure used to indicate the depth of the DATA fi ...

  • Page 76

    Start and complete split for isochronous Table 75 shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD). Table 75. Start and complete split for isochronous: bit allocation Bit ...

  • Page 77

    ... NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] HW — writes ISO_IN_4[7:0] HW — writes ISO_IN_3[7:0] HW — writes DW5 ISO_IN_2[7:0] HW — writes ISO_IN_1[7:0] HW — writes ISO_IN_0[7:0] HW — writes ...

  • Page 78

    ... NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — ...

  • Page 79

    ... NXP Semiconductors Table 76. Start and complete split for isochronous: bit description Bit Symbol Access Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved - TT_MPS_Len SW — writes [10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets ISP1760_4 ...

  • Page 80

    Start and complete split for interrupt Table 77 shows the bit allocation of start and complete split for interrupt. Table 77. Start and complete split for interrupt: bit allocation Bit ...

  • Page 81

    ... NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — writes INT_IN_4[7:0] HW — writes INT_IN_3[7:0] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[7:0] HW — writes INT_IN_0[7:0] HW — writes ...

  • Page 82

    ... NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access Status0[2:0] HW — writes SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates ...

  • Page 83

    ... NXP Semiconductors Table 78. Start and complete split for interrupt: bit description Bit Symbol Access PortNumber[6:0] SW — writes SE[1:0] SW — writes 47 reserved - — writes EPType[1:0] SW — writes Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved - MaxPacketLength SW — ...

  • Page 84

    ... NXP Semiconductors Table 80. Interrupt I/O I/O ISP1760_4 Product data sheet SE description Rev. 04 — 4 February 2008 ISP1760 Embedded Hi-Speed USB host controller E Remarks 0 low-speed 0 full-speed © NXP B.V. 2008. All rights reserved 110 ...

  • Page 85

    ... NXP Semiconductors 10. Power consumption Table 81. Number of ports working One port working (high-speed Two ports working (high-speed Three ports working (high-speed The idle operating current, I initialized and without any devices connected mA. The additional current consumption on I devices. ...

  • Page 86

    ... NXP Semiconductors 11. Limiting values Table 82. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage (5.0 V) CC(5V0) I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg 12. Recommended operating conditions Table 83. ...

  • Page 87

    ... NXP Semiconductors 13. Static characteristics Table 84. Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; T Symbol Parameter 1.95 V CC(I/O) V HIGH-level input voltage ...

  • Page 88

    ... NXP Semiconductors Table 86. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter V high-speed data signaling HSOH HIGH-level voltage V high-speed data signaling HSOL LOW-level voltage V Chirp J level (differential voltage) CHIRPJ ...

  • Page 89

    ... NXP Semiconductors 14. Dynamic characteristics Table 88. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input t external clock jitter J clock duty cycle V input voltage on pin XTAL1 i(XTAL1) t rise time ...

  • Page 90

    ... NXP Semiconductors Table 91. Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Driver characteristics t rise time FR t fall time FF t differential rise and fall time FRFM matching Z driver output impedance DRV Data timing: see ...

  • Page 91

    ... NXP Semiconductors 14.1 PIO timing 14.1.1 Register or memory write Fig 15. Register or memory write Table 93 +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t h11 t h21 t h31 t w11 t su11 t su21 t su31 3.6 V CC(I/O) t h11 t h21 t h31 t w11 t su11 t su21 t su31 ...

  • Page 92

    ... NXP Semiconductors 14.1.2 Register read Fig 16. Register read Table 94 +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t d22 3.6 V CC(I/O) t su12 t su22 t w12 t d12 t d22 14.1.3 Register access CS_N WR_N RD_N Fig 17. Register access ...

  • Page 93

    ... NXP Semiconductors Table 95 +85 C; unless otherwise specified. amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 14.1.4 Memory read A[17:1] DATA CS_N WR_N RD_N Fig 18. Memory read Table 96 +85 C; unless otherwise specified. amb Symbol 1.95 V ...

  • Page 94

    ... NXP Semiconductors Table 96 +85 C; unless otherwise specified. amb Symbol t d23 t w13 t su13 t su23 14.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH. 14.2.1 Single cycle: DMA read Fig 19. DMA read (single cycle) Table 97. ...

  • Page 95

    ... NXP Semiconductors Table 97 +85 C; unless otherwise specified. amb Symbol t w14 t a34 t a44 t h14 14.2.2 Single cycle: DMA write Fig 20. DMA write (single cycle) Table 98 +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) t a15 t a25 t h15 t h25 t su15 ...

  • Page 96

    ... NXP Semiconductors 14.2.3 Multi-cycle: DMA read Fig 21. DMA read (multi-cycle burst) Table 99 +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) t a16 t a26 t d16 t w16 T cy16 t a36 t a46 t h16 3.6 V CC(I/O) t a16 t a26 t d16 t w16 T cy16 t a36 t a46 ...

  • Page 97

    ... NXP Semiconductors 14.2.4 Multi-cycle: DMA write Fig 22. DMA write (multi-cycle burst) Table 100. DMA write (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) T cy17 t su17 t h17 t a17 t a27 t a37 t h27 t a47 t w17 t a57 3.6 V CC(I/O) ...

  • Page 98

    ... NXP Semiconductors 15. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 99

    ... NXP Semiconductors TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 0.8 mm ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.85 0.35 mm 1.1 0.15 0.75 0.25 OUTLINE VERSION IEC SOT857-1 Fig 24. Package outline SOT857-1 (TFBGA128) ...

  • Page 100

    ... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 101

    ... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

  • Page 102

    ... NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Soldering of through-hole mount packages 17.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. ...

  • Page 103

    ... NXP Semiconductors 17.4 Package related soldering information Table 103. Suitability of through-hole mount IC packages for dipping and wave soldering Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board ...

  • Page 104

    ... NXP Semiconductors Table 104. Abbreviations Acronym OC OHCI PCI PDA PID PIO PLL PMOS POR PORP PTD RISC SE0 SE1 siTD SOF SRP SS TT UHCI USB 19. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 ...

  • Page 105

    ... NXP Semiconductors 20. Revision history Table 105. Revision history Document ID Release date ISP1760_4 20080204 • Modifications: Section 7.3 “Accessing the ISP1760 host controller memory: PIO and paragraph. • Table 52 “Power Down Control register (address 0354h) bit bits 12 and 11. • Table 82 “Limiting • ...

  • Page 106

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 107

    ... NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 3. Port connection scenarios . . . . . . . . . . . . . . . .15 Table 4. Memory address . . . . . . . . . . . . . . . . . . . . . . .17 Table 5. Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 6. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 7. Pin status in hybrid mode . . . . . . . . . . . . . . . .27 Table 8. Register overview . . . . . . . . . . . . . . . . . . . . . .29 Table 9. CAPLENGTH - Capability Length register (address 0000h) bit description ...

  • Page 108

    ... NXP Semiconductors Table 57. Interrupt Enable register (address 0314h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 58. Interrupt Enable register (address 0314h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 59. ISO IRQ Mask OR register (address 0318h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 60. INT IRQ Mask OR register (address 031Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 61. ATL IRQ Mask OR register (address 0320h) bit description ...

  • Page 109

    ... NXP Semiconductors 24. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration (LQFP128); top view . . . . . . . . .5 Fig 3. Pin configuration (TFBGA128); top view . . . . . . . .5 Fig 4. Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Fig 5. ISP1760 clock scheme . . . . . . . . . . . . . . . . . . . .14 Fig 6. Memory segmentation and access block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Fig 7. Adjusting analog overcurrent detection limit (optional .25 Fig 8 ...

  • Page 110

    ... NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 Examples of a multitude of possible applications Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 13 7.1 ISP1760 internal architecture: advanced NXP slave host controller and hub . . . . . . . . . 13 7 ...

  • Page 111

    ... NXP Semiconductors 17.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . 101 17.4 Package related soldering information . . . . . 102 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 104 21 Legal information 105 21.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 105 21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 105 22 Contact information 105 23 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 24 Figures ...