ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 52.
[1]
Bit
2
1
0
[1]
For a 32-bit operation, the default wake-up counter value is 10 s. For a 16-bit operation, the wake-up
counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
8.3.12 Port 1 Control register
The values read from the lower 16 bits and the upper 16 bits of this register are always the
same.
Table 53
Table 53.
Port 1 Control register (address 0374h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
PORT1_
INIT2
Reset
1
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
Bit
7
Symbol
PORT1_
INIT1
Reset
0
Access
R/W
R/W
ISP1760_4
Product data sheet
Power Down Control register (address 0354h) bit description
Symbol
Description
OC2_PWR
OC2_N Powered: Controls the powering of the overcurrent detection
circuitry for port 2.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in
standby.
OC1_PWR
OC1_N Powered: Controls the powering of the overcurrent detection
circuitry for port 1.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in
standby.
HC_CLK_
Host Controller Clock Enabled: Controls internal clocks during suspend.
EN
0 — Clocks are disabled during suspend. This is the default value. Only
the LazyClock of 100 kHz
is logic 0. If clocks are stopped during suspend, CLKREADY IRQ will be
generated when all clocks are running stable.
1 — All clocks are enabled even in suspend.
shows the bit allocation of the register.
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
0
0
0
R/W
R/W
14
13
12
reserved
0
0
0
R/W
R/W
6
5
4
reserved
PORT1_POWER[1:0]
0
0
1
R/W
R/W
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
…continued
40 % will be left running in suspend if this bit
27
26
25
0
0
0
R/W
R/W
R/W
19
18
17
reserved
0
1
1
R/W
R/W
R/W
11
10
9
0
0
0
R/W
R/W
R/W
3
2
1
reserved
0
1
1
R/W
R/W
R/W
© NXP B.V. 2008. All rights reserved.
ISP1760
24
0
R/W
16
0
R/W
8
0
R/W
0
0
R/W
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