ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 56.
Bit
2
1
0
8.4.2 Interrupt Enable register
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Table 57.
Interrupt Enable register (address 0314h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
Bit
7
Symbol
INT_IRQ_E CLKREADY
_E
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
ISP1760_4
Product data sheet
Interrupt register (address 0310h) bit description
Symbol
Description
-
reserved; write reset value; value is zero just after reset and changes to
one after a short while
SOFITLINT
SOT ITL Interrupt: The IRQ line will be asserted if the respective enable
bit in the HCInterruptEnable register is set.
0 — No SOF event has occurred.
1 — An SOF event has occurred.
-
reserved; write reset value; value is zero just after reset and changes to
one after a short while
Table
57.
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
reserved
0
0
0
R/W
R/W
14
13
12
[1]
reserved
0
0
0
R/W
R/W
6
5
4
[1]
HCSUSP_E
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
…continued
27
26
25
[1]
0
0
0
R/W
R/W
R/W
19
18
17
[1]
0
0
0
R/W
R/W
R/W
11
10
9
ISO_IRQ_E
0
0
0
R/W
R/W
R/W
3
2
1
[1]
DMAEOT
reserved
SOFITLINT
INT_E
_E
0
0
0
R/W
R/W
R/W
© NXP B.V. 2008. All rights reserved.
ISP1760
24
0
R/W
16
0
R/W
8
ATL_IRQ
_E
0
R/W
0
[1]
reserved
0
R/W
53 of 110