ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 54
ISP1760ET,557
Manufacturer Part Number
ISP1760ET,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1760ET557.pdf
(111 pages)
Specifications of ISP1760ET,557
Package Type
TFBGA
Pin Count
128
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
Table 57.
[1]
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Interrupt Enable register (address 0314h) bit allocation
INT_IRQ_E CLKREADY
8.4.2 Interrupt Enable register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 56.
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Bit
2
1
0
R/W
R/W
R/W
R/W
_E
30
22
14
0
0
0
6
0
Symbol
-
SOFITLINT
-
Interrupt register (address 0310h) bit description
HCSUSP_E
Table
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
57.
Rev. 04 — 4 February 2008
reserved
Description
reserved; write reset value; value is zero just after reset and changes to
one after a short while
SOT ITL Interrupt: The IRQ line will be asserted if the respective enable
bit in the HCInterruptEnable register is set.
0 — No SOF event has occurred.
1 — An SOF event has occurred.
reserved; write reset value; value is zero just after reset and changes to
one after a short while
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
[1]
DMAEOT
[1]
[1]
INT_E
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
reserved
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
…continued
[1]
ISO_IRQ_E
SOFITLINT
R/W
R/W
R/W
R/W
_E
25
17
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1760
reserved
ATL_IRQ
R/W
R/W
R/W
R/W
_E
53 of 110
24
16
0
0
8
0
0
0
[1]
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