ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 57. Interrupt Enable register (address 0314h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 58. Interrupt Enable register (address 0314h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 59. ISO IRQ Mask OR register (address 0318h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 60. INT IRQ Mask OR register (address 031Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 61. ATL IRQ Mask OR register (address 0320h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 62. ISO IRQ Mask AND register (address 0324h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 63. INT IRQ Mask AND register (address 0328h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 64. ATL IRQ Mask AND register (address 032Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 65. High-speed bulk IN and OUT:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 66. High-speed bulk IN and OUT:
bit description . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 67. High-speed isochronous IN and OUT:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 68. High-speed isochronous IN and OUT:
bit description . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 69. High-speed interrupt IN and OUT:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 70. High-speed interrupt IN and OUT:
bit description . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 71. Microframe description . . . . . . . . . . . . . . . . . .70
Table 72. Start and complete split for bulk:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 73. Start and complete split for bulk:
bit description . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 74. SE description . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 75. Start and complete split for isochronous:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 76. Start and complete split for isochronous:
bit description . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 77. Start and complete split for interrupt:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 78. Start and complete split for interrupt:
bit description . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 79. Microframe description . . . . . . . . . . . . . . . . . .82
Table 80. SE description . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 81. Power consumption . . . . . . . . . . . . . . . . . . . . .84
Table 82. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 83. Recommended operating conditions . . . . . . . .85
Table 84. Static characteristics: digital pins . . . . . . . . . . .86
Table 85. Static characteristics:
PSW1_N, PSW2_N, PSW3_N . . . . . . . . . . . .86
Table 86. Static characteristics: USB interface block
(pins DM1 to DM3 and DP1 to DP3) . . . . . . . .86
Table 87. Static characteristics: REF5V . . . . . . . . . . . . .87
Table 88. Dynamic characteristics: system clock
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 89. Dynamic characteristics: CPU interface
block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 90. Dynamic characteristics: high-speed
ISP1760_4
Product data sheet
Embedded Hi-Speed USB host controller
source electrical characteristics . . . . . . . . . . . 88
Table 91. Dynamic characteristics: full-speed source
electrical characteristics . . . . . . . . . . . . . . . . . 89
Table 92. Dynamic characteristics: low-speed
source electrical characteristics . . . . . . . . . . . 89
Table 93. Register or memory write . . . . . . . . . . . . . . . . 90
Table 94. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 95. Register access . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 96. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 97. DMA read (single cycle) . . . . . . . . . . . . . . . . . 93
Table 98. DMA write (single cycle) . . . . . . . . . . . . . . . . . 94
Table 99. DMA read (multi-cycle burst) . . . . . . . . . . . . . . 95
Table 100.DMA write (multi-cycle burst) . . . . . . . . . . . . . 96
Table 101.SnPb eutectic process (from J-STD-020C) . . 100
Table 102.Lead-free process (from J-STD-020C) . . . . . 100
Table 103.Suitability of through-hole mount
IC packages for dipping and wave soldering . 102
Table 104.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 105.Revision history . . . . . . . . . . . . . . . . . . . . . . . 104
Rev. 04 — 4 February 2008
ISP1760
© NXP B.V. 2008. All rights reserved.
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