ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 56.
Bit
31 to 10 -
9
8
7
6
5
4
3
ISP1760_4
Product data sheet
Interrupt register (address 0310h) bit description
Symbol
Description
reserved; write reset value
ISO_IRQ
ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs
corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask
OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HCInterruptEnable register is
set.
0 — No ISO PTD event occurred.
1 — ISO PTD event occurred.
For details, see
Section
ATL_IRQ
ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs
corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ Mask
OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HCInterruptEnable register is
set.
0 — No ATL PTD event occurred.
1 — ATL PTD event occurred.
For details, see
Section
INT_IRQ
INT IRQ: Indicates that an INT PTD was completed, or the PTDs
corresponding to the bits set in the INT IRQ Mask AND or INT IRQ Mask
OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HCInterruptEnable register is
set.
0 — No INT PTD event occurred.
1 — INT PTD event occurred.
For details, see
Section
CLKREADY
Clock Ready: Indicates that internal clock signals are running stable. The
IRQ line will be asserted if the respective enable bit in the
HCInterruptEnable register is set.
0 — No CLKREADY event has occurred.
1 — CLKREADY event occurred.
HC_SUSP
Host Controller Suspend: Indicates that the host controller has entered
suspend mode. The IRQ line will be asserted if the respective enable bit
in the HCInterruptEnable register is set.
0 — The host controller did not enter suspend mode.
1 — The host controller entered suspend mode.
If the ISR accesses the ISP1760, it will wake up for the time specified in
bits 31 to 16 of the Power Down Control register.
-
reserved; write reset value
DMAEOT
DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ line
INT
will be asserted if the respective enable bit in the HCInterruptEnable
register is set.
0 — No DMA transfer is completed.
1 — DMA transfer is complete.
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
7.4.
7.4.
7.4.
© NXP B.V. 2008. All rights reserved.
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