ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
Table 6.
Voltage
V
CC(5V0)
V
CC(I/O)
In hybrid mode (see
transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the
suspend current, I
V
CC(5V0)
back on, before the resume programming sequence starts.
Fig 10. Hybrid mode
Table 7
Table 7.
Pins
DATA[31:0], A[17:1], TEST1, TEST2, TEST3,
TEST4, TEST5, TEST6, TEST7, DREQ,
DACK, IRQ, SUSPEND/WAKEUP_N
CS_N, RESET_N, RD_N, WR_N
7.9 Power-On Reset (POR)
When V
t
, will typically be 800 ns. The pulse is started when V
PORP
1.2 V.
ISP1760_4
Product data sheet
Hybrid mode
Figure
10), V
CC(5V0)
, below 100 A. If the ISP1760 is used in hybrid mode and
CC(I/O)
is off during suspend, a 2 ms reset pulse is required when power is switched
ISP1760BE
V
CC(5V0)
6, 7
10, 40, 48,
V
CC(I/O)
59, 67, 75,
83, 94,
104, 115
REG1V8
85
REG1V8
5, 50, 118
REG3V3
9
The figure shows the LQFP pinout. For the TFBGA ballout, see
A 4.7 F-to-10 F electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.
All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2
shows the status of output pins during hybrid mode.
Pin status in hybrid mode
is directly connected to the RESET_N pin, the internal POR pulse width,
CC(I/O)
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
Status
off
on
can be switched off using an external PMOS
controlled by the CPU
3.3 V to 5 V
100 nF
1.65 V to 3.6 V
100 nF
100 nF
10 µF
100 nF
100 nF
10 µF
004aaa677
Table
2.
V
V
CC(I/O)
CC(5V0)
on
on
on
off
off
X
on
X
off
X
rises above V
CC(5V0)
ISP1760
to 2 ).
Status
normal
high-Z
undefined
input
undefined
of
TRIP
© NXP B.V. 2008. All rights reserved.
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