ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
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NXP Semiconductors
Table 58.
Bit
31 to 10
9
8
7
6
5
4
3
2
1
0
8.4.3 ISO IRQ Mask OR register
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Section
ISP1760_4
Product data sheet
Interrupt Enable register (address 0314h) bit description
Symbol
Description
-
reserved; write logic 0
ISO_IRQ_E
ISO IRQ Enable: Controls the IRQ assertion when one or more ISO
PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR
register bits combination are completed.
0 — No IRQ will be asserted when ISO PTDs are completed.
1 — IRQ will be asserted.
For details, see
ATL_IRQ_E
ATL IRQ Enable: Controls the IRQ assertion when one or more ATL
PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR
register bits combination are completed.
0 — No IRQ will be asserted when ATL PTDs are completed.
1 — IRQ will be asserted.
For details, see
INT_IRQ_E
INT IRQ Enable: Controls the IRQ assertion when one or more INT
PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register
bits combination are completed.
0 — No IRQ will be asserted when INT PTDs are completed.
1 — IRQ will be asserted.
For details, see
CLKREADY_
Clock Ready Enable: Enables the IRQ assertion when internal clock
E
signals are running stable. Useful after wake-up.
0 — No IRQ will be generated after a CLKREADY_E event.
1 — IRQ will be generated after a CLKREADY_E event.
HCSUSP_E
Host Controller Suspend Enable: Enables the IRQ generation
when the host controller enters suspend mode.
0 — No IRQ will be generated when the host controller enters
suspend mode.
1 — IRQ will be generated when the host controller enters suspend
mode.
-
reserved; write logic 0
DMAEOTINT
DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA
_E
transfer completion.
0 — No IRQ will be generated when a DMA transfer is completed.
1 — IRQ will be asserted when a DMA transfer is completed.
-
reserved; must be written with logic 0
SOFITLINT_
SOT ITL Interrupt Enable: Controls the IRQ generation at every
E
SOF occurrence.
0 — No IRQ will be generated on an SOF occurrence.
1 — IRQ will be asserted at every SOF.
-
reserved; must be written with logic 0
7.4.
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
Section
7.4.
Section
7.4.
Section
7.4.
Table 59
for bit description. For details,
ISP1760
© NXP B.V. 2008. All rights reserved.
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