ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 29
Manufacturer Part Number
Specifications of ISP1760ET,557
Lead Free Status / RoHS Status
Product data sheet
To give a better view of the functionality,
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short, that is, < 11 s, the internal
POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1,
the detector will see the passing of the trip level and a delay element will add another
The internal POR pulse will be generated whenever V
than 11 s.
The recommended RESET input pulse length at power-on must be at least 2 ms to ensure
that internal clocks are stable.
The RESET_N pin can be either connected to V
externally controlled by the microcontroller, ASIC, and so on.
availability of the clock with respect to the external POR.
Fig 11. Internal power-on reset timing
Fig 12. Clock with respect to the external power-on reset
before it drops to 0.
(1) PORP = Power-On Reset Pulse.
Stable external clock is available at A.
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
shows a possible curve of V
using the internal POR circuit or
drops below V
© NXP B.V. 2008. All rights reserved.
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