ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 


Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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NXP Semiconductors
To give a better view of the functionality,
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short, that is, < 11 s, the internal
POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1,
the detector will see the passing of the trip level and a delay element will add another
t
before it drops to 0.
PORP
The internal POR pulse will be generated whenever V
than 11 s.
Fig 11. Internal power-on reset timing
The recommended RESET input pulse length at power-on must be at least 2 ms to ensure
that internal clocks are stable.
The RESET_N pin can be either connected to V
externally controlled by the microcontroller, ASIC, and so on.
availability of the clock with respect to the external POR.
Fig 12. Clock with respect to the external power-on reset
ISP1760_4
Product data sheet
Figure 11
t0
t1
t2
t
PORP
(1) PORP = Power-On Reset Pulse.
RESET_N
EXTERNAL CLOCK
Stable external clock is available at A.
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
shows a possible curve of V
drops below V
CC(5V0)
TRIP
V
CC(5V0)
V
TRIP
t4
t3
t5
PORP
t
PORP
004aaa584
using the internal POR circuit or
CC(I/O)
Figure 12
shows the
004aaa583
A
© NXP B.V. 2008. All rights reserved.
with
CC(5V0)
for more
(1)
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