ISP1760ET,557

Manufacturer Part NumberISP1760ET,557
ManufacturerNXP Semiconductors
ISP1760ET,557 datasheet
 

Specifications of ISP1760ET,557

Package TypeTFBGAPin Count128
Lead Free Status / RoHS StatusCompliant  
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Page 47/111

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NXP Semiconductors
Table 45.
Memory register (address 033Ch) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
Bit
15
Symbol
Reset
0
Access
R/W
R/W
Bit
7
Symbol
Reset
0
Access
R/W
R/W
[1]
The reserved bits should always be written with the reset value.
Table 46.
Bit
31 to 18
17 to 16
15 to 0
8.3.9 Edge Interrupt Count register
Table 47
Table 47.
Edge Interrupt Count register (address 0340h) bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
R/W
Bit
23
Symbol
Reset
0
Access
R/W
R/W
ISP1760_4
Product data sheet
30
29
28
reserved
0
0
0
R/W
R/W
22
21
20
[1]
reserved
0
0
0
R/W
R/W
14
13
12
START_ADDR_MEM_READ[15:8]
0
0
0
R/W
R/W
6
5
4
START_ADDR_MEM_READ[7:0]
0
0
0
R/W
R/W
Memory register (address 033Ch) bit description
Symbol
Description
-
reserved
MEM_BANK_
Memory Bank Select: Up to four memory banks can be selected.
SEL[1:0]
For details on internal memory read description, see
Applicable to PIO mode memory read or write data transfers only.
START_ADDR
Start Address for Memory Read Cycles: The start address for a
_MEM_READ
series of memory read cycles at incremental addresses in a
[15:0]
contiguous space. Applicable to PIO mode memory read data
transfers only.
shows the bit allocation of the register.
30
29
28
MIN_WIDTH[7:0]
0
0
0
R/W
R/W
22
21
20
reserved
0
0
0
R/W
R/W
Rev. 04 — 4 February 2008
ISP1760
Embedded Hi-Speed USB host controller
27
26
25
[1]
0
0
0
R/W
R/W
R/W
19
18
17
MEM_BANK_SEL[1:0]
0
0
0
R/W
R/W
R/W
11
10
9
0
0
0
R/W
R/W
R/W
3
2
1
0
0
0
R/W
R/W
R/W
27
26
25
0
0
0
R/W
R/W
R/W
19
18
17
[1]
0
0
0
R/W
R/W
R/W
© NXP B.V. 2008. All rights reserved.
24
0
R/W
16
0
R/W
8
0
R/W
0
0
R/W
Section
7.3.1.
24
0
R/W
16
0
R/W
46 of 110